51007004f4
In general we want to avoid ever touching memory while within an interrupt critical section, since the page fault path goes through a different path from the hypervisor when in an interrupt critical section, and we carefully decided with tilegx that we didn't need to support this path in the kernel. (On tilepro we did implement that path as part of supporting atomic instructions in software.) In practice we always need to touch the kernel stack, since that's where we store the interrupt state before releasing the critical section, but this change cleans up a few things. The IRQ_ENABLE macro is split up so that when we want to enable interrupts in a deferred way (e.g. for cpu_idle or for interrupt return) we can read the per-cpu enable mask before entering the critical section. The cache-migration code is changed to use interrupt masking instead of interrupt critical sections. And, the interrupt-entry code is changed so that we defer loading "tp" from per-cpu data until after we have released the interrupt critical section. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
57 lines
1.9 KiB
C
57 lines
1.9 KiB
C
/*
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* Copyright 2010 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*
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* Structure definitions for migration, exposed here for use by
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* arch/tile/kernel/asm-offsets.c.
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*/
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#ifndef MM_MIGRATE_H
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#define MM_MIGRATE_H
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#include <linux/cpumask.h>
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#include <hv/hypervisor.h>
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/*
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* This function is used as a helper when setting up the initial
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* page table (swapper_pg_dir).
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*
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* You must mask ALL interrupts prior to invoking this code, since
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* you can't legally touch the stack during the cache flush.
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*/
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extern int flush_and_install_context(HV_PhysAddr page_table, HV_PTE access,
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HV_ASID asid,
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const unsigned long *cpumask);
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/*
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* This function supports migration as a "helper" as follows:
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*
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* - Set the stack PTE itself to "migrating".
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* - Do a global TLB flush for (va,length) and the specified ASIDs.
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* - Do a cache-evict on all necessary cpus.
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* - Write the new stack PTE.
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*
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* Note that any non-NULL pointers must not point to the page that
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* is handled by the stack_pte itself.
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*
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* You must mask ALL interrupts prior to invoking this code, since
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* you can't legally touch the stack during the cache flush.
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*/
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extern int homecache_migrate_stack_and_flush(pte_t stack_pte, unsigned long va,
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size_t length, pte_t *stack_ptep,
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const struct cpumask *cache_cpumask,
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const struct cpumask *tlb_cpumask,
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HV_Remote_ASID *asids,
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int asidcount);
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#endif /* MM_MIGRATE_H */
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