![Ville Syrjälä](/assets/img/avatar_default.png)
Let's be a bit more consistent with our error values. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
611 lines
16 KiB
C
611 lines
16 KiB
C
/*
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* Copyright © 2006-2011 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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*/
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#include <linux/i2c.h>
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#include <drm/drmP.h>
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#include "framebuffer.h"
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#include "psb_drv.h"
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#include "psb_intel_drv.h"
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#include "psb_intel_reg.h"
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#include "gma_display.h"
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#include "power.h"
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#define INTEL_LIMIT_I9XX_SDVO_DAC 0
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#define INTEL_LIMIT_I9XX_LVDS 1
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static const struct gma_limit_t psb_intel_limits[] = {
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{ /* INTEL_LIMIT_I9XX_SDVO_DAC */
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.dot = {.min = 20000, .max = 400000},
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.vco = {.min = 1400000, .max = 2800000},
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.n = {.min = 1, .max = 6},
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.m = {.min = 70, .max = 120},
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.m1 = {.min = 8, .max = 18},
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.m2 = {.min = 3, .max = 7},
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.p = {.min = 5, .max = 80},
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.p1 = {.min = 1, .max = 8},
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.p2 = {.dot_limit = 200000, .p2_slow = 10, .p2_fast = 5},
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.find_pll = gma_find_best_pll,
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},
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{ /* INTEL_LIMIT_I9XX_LVDS */
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.dot = {.min = 20000, .max = 400000},
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.vco = {.min = 1400000, .max = 2800000},
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.n = {.min = 1, .max = 6},
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.m = {.min = 70, .max = 120},
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.m1 = {.min = 8, .max = 18},
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.m2 = {.min = 3, .max = 7},
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.p = {.min = 7, .max = 98},
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.p1 = {.min = 1, .max = 8},
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/* The single-channel range is 25-112Mhz, and dual-channel
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* is 80-224Mhz. Prefer single channel as much as possible.
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*/
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.p2 = {.dot_limit = 112000, .p2_slow = 14, .p2_fast = 7},
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.find_pll = gma_find_best_pll,
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},
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};
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static const struct gma_limit_t *psb_intel_limit(struct drm_crtc *crtc,
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int refclk)
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{
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const struct gma_limit_t *limit;
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if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
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limit = &psb_intel_limits[INTEL_LIMIT_I9XX_LVDS];
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else
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limit = &psb_intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC];
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return limit;
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}
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static void psb_intel_clock(int refclk, struct gma_clock_t *clock)
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{
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clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
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clock->p = clock->p1 * clock->p2;
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clock->vco = refclk * clock->m / (clock->n + 2);
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clock->dot = clock->vco / clock->p;
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}
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/**
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* Return the pipe currently connected to the panel fitter,
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* or -1 if the panel fitter is not present or not in use
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*/
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static int psb_intel_panel_fitter_pipe(struct drm_device *dev)
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{
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u32 pfit_control;
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pfit_control = REG_READ(PFIT_CONTROL);
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/* See if the panel fitter is in use */
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if ((pfit_control & PFIT_ENABLE) == 0)
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return -1;
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/* Must be on PIPE 1 for PSB */
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return 1;
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}
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static int psb_intel_crtc_mode_set(struct drm_crtc *crtc,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode,
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int x, int y,
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struct drm_framebuffer *old_fb)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_psb_private *dev_priv = dev->dev_private;
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struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
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struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
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int pipe = gma_crtc->pipe;
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const struct psb_offset *map = &dev_priv->regmap[pipe];
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int refclk;
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struct gma_clock_t clock;
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u32 dpll = 0, fp = 0, dspcntr, pipeconf;
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bool ok, is_sdvo = false;
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bool is_lvds = false, is_tv = false;
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struct drm_mode_config *mode_config = &dev->mode_config;
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struct drm_connector *connector;
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const struct gma_limit_t *limit;
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/* No scan out no play */
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if (crtc->fb == NULL) {
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crtc_funcs->mode_set_base(crtc, x, y, old_fb);
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return 0;
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}
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list_for_each_entry(connector, &mode_config->connector_list, head) {
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struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
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if (!connector->encoder
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|| connector->encoder->crtc != crtc)
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continue;
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switch (gma_encoder->type) {
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case INTEL_OUTPUT_LVDS:
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is_lvds = true;
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break;
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case INTEL_OUTPUT_SDVO:
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is_sdvo = true;
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break;
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case INTEL_OUTPUT_TVOUT:
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is_tv = true;
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break;
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}
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}
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refclk = 96000;
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limit = gma_crtc->clock_funcs->limit(crtc, refclk);
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ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk,
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&clock);
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if (!ok) {
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DRM_ERROR("Couldn't find PLL settings for mode! target: %d, actual: %d",
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adjusted_mode->clock, clock.dot);
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return 0;
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}
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fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
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dpll = DPLL_VGA_MODE_DIS;
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if (is_lvds) {
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dpll |= DPLLB_MODE_LVDS;
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dpll |= DPLL_DVO_HIGH_SPEED;
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} else
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dpll |= DPLLB_MODE_DAC_SERIAL;
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if (is_sdvo) {
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int sdvo_pixel_multiply =
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adjusted_mode->clock / mode->clock;
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dpll |= DPLL_DVO_HIGH_SPEED;
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dpll |=
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(sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
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}
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/* compute bitmask from p1 value */
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dpll |= (1 << (clock.p1 - 1)) << 16;
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switch (clock.p2) {
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case 5:
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dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
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break;
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case 7:
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dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
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break;
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case 10:
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dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
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break;
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case 14:
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dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
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break;
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}
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if (is_tv) {
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/* XXX: just matching BIOS for now */
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/* dpll |= PLL_REF_INPUT_TVCLKINBC; */
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dpll |= 3;
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}
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dpll |= PLL_REF_INPUT_DREFCLK;
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/* setup pipeconf */
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pipeconf = REG_READ(map->conf);
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/* Set up the display plane register */
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dspcntr = DISPPLANE_GAMMA_ENABLE;
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if (pipe == 0)
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dspcntr |= DISPPLANE_SEL_PIPE_A;
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else
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dspcntr |= DISPPLANE_SEL_PIPE_B;
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dspcntr |= DISPLAY_PLANE_ENABLE;
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pipeconf |= PIPEACONF_ENABLE;
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dpll |= DPLL_VCO_ENABLE;
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/* Disable the panel fitter if it was on our pipe */
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if (psb_intel_panel_fitter_pipe(dev) == pipe)
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REG_WRITE(PFIT_CONTROL, 0);
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drm_mode_debug_printmodeline(mode);
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if (dpll & DPLL_VCO_ENABLE) {
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REG_WRITE(map->fp0, fp);
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REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE);
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REG_READ(map->dpll);
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udelay(150);
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}
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/* The LVDS pin pair needs to be on before the DPLLs are enabled.
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* This is an exception to the general rule that mode_set doesn't turn
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* things on.
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*/
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if (is_lvds) {
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u32 lvds = REG_READ(LVDS);
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lvds &= ~LVDS_PIPEB_SELECT;
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if (pipe == 1)
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lvds |= LVDS_PIPEB_SELECT;
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lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
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/* Set the B0-B3 data pairs corresponding to
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* whether we're going to
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* set the DPLLs for dual-channel mode or not.
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*/
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lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
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if (clock.p2 == 7)
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lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
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/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
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* appropriately here, but we need to look more
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* thoroughly into how panels behave in the two modes.
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*/
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REG_WRITE(LVDS, lvds);
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REG_READ(LVDS);
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}
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REG_WRITE(map->fp0, fp);
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REG_WRITE(map->dpll, dpll);
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REG_READ(map->dpll);
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/* Wait for the clocks to stabilize. */
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udelay(150);
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/* write it again -- the BIOS does, after all */
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REG_WRITE(map->dpll, dpll);
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REG_READ(map->dpll);
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/* Wait for the clocks to stabilize. */
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udelay(150);
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REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) |
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((adjusted_mode->crtc_htotal - 1) << 16));
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REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) |
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((adjusted_mode->crtc_hblank_end - 1) << 16));
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REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) |
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((adjusted_mode->crtc_hsync_end - 1) << 16));
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REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) |
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((adjusted_mode->crtc_vtotal - 1) << 16));
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REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) |
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((adjusted_mode->crtc_vblank_end - 1) << 16));
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REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) |
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((adjusted_mode->crtc_vsync_end - 1) << 16));
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/* pipesrc and dspsize control the size that is scaled from,
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* which should always be the user's requested size.
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*/
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REG_WRITE(map->size,
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((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
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REG_WRITE(map->pos, 0);
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REG_WRITE(map->src,
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((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
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REG_WRITE(map->conf, pipeconf);
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REG_READ(map->conf);
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gma_wait_for_vblank(dev);
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REG_WRITE(map->cntr, dspcntr);
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/* Flush the plane changes */
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crtc_funcs->mode_set_base(crtc, x, y, old_fb);
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gma_wait_for_vblank(dev);
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return 0;
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}
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/* Returns the clock of the currently programmed mode of the given pipe. */
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static int psb_intel_crtc_clock_get(struct drm_device *dev,
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struct drm_crtc *crtc)
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{
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struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
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struct drm_psb_private *dev_priv = dev->dev_private;
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int pipe = gma_crtc->pipe;
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const struct psb_offset *map = &dev_priv->regmap[pipe];
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u32 dpll;
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u32 fp;
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struct gma_clock_t clock;
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bool is_lvds;
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struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
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if (gma_power_begin(dev, false)) {
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dpll = REG_READ(map->dpll);
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if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
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fp = REG_READ(map->fp0);
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else
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fp = REG_READ(map->fp1);
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is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN);
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gma_power_end(dev);
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} else {
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dpll = p->dpll;
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if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
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fp = p->fp0;
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else
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fp = p->fp1;
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is_lvds = (pipe == 1) && (dev_priv->regs.psb.saveLVDS &
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LVDS_PORT_EN);
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}
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clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
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clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
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clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
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if (is_lvds) {
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clock.p1 =
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ffs((dpll &
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DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
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DPLL_FPA01_P1_POST_DIV_SHIFT);
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clock.p2 = 14;
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if ((dpll & PLL_REF_INPUT_MASK) ==
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PLLB_REF_INPUT_SPREADSPECTRUMIN) {
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/* XXX: might not be 66MHz */
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psb_intel_clock(66000, &clock);
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} else
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psb_intel_clock(48000, &clock);
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} else {
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if (dpll & PLL_P1_DIVIDE_BY_TWO)
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clock.p1 = 2;
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else {
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clock.p1 =
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((dpll &
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DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
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DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
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}
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if (dpll & PLL_P2_DIVIDE_BY_4)
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clock.p2 = 4;
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else
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clock.p2 = 2;
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psb_intel_clock(48000, &clock);
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}
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/* XXX: It would be nice to validate the clocks, but we can't reuse
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* i830PllIsValid() because it relies on the xf86_config connector
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* configuration being accurate, which it isn't necessarily.
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*/
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return clock.dot;
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}
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/** Returns the currently programmed mode of the given pipe. */
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struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev,
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struct drm_crtc *crtc)
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{
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struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
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int pipe = gma_crtc->pipe;
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struct drm_display_mode *mode;
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int htot;
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int hsync;
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int vtot;
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int vsync;
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struct drm_psb_private *dev_priv = dev->dev_private;
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struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
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const struct psb_offset *map = &dev_priv->regmap[pipe];
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if (gma_power_begin(dev, false)) {
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htot = REG_READ(map->htotal);
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hsync = REG_READ(map->hsync);
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vtot = REG_READ(map->vtotal);
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vsync = REG_READ(map->vsync);
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gma_power_end(dev);
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} else {
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htot = p->htotal;
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hsync = p->hsync;
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vtot = p->vtotal;
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vsync = p->vsync;
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}
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mode = kzalloc(sizeof(*mode), GFP_KERNEL);
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if (!mode)
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return NULL;
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mode->clock = psb_intel_crtc_clock_get(dev, crtc);
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mode->hdisplay = (htot & 0xffff) + 1;
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mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
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mode->hsync_start = (hsync & 0xffff) + 1;
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mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
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mode->vdisplay = (vtot & 0xffff) + 1;
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mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
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mode->vsync_start = (vsync & 0xffff) + 1;
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mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
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drm_mode_set_name(mode);
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drm_mode_set_crtcinfo(mode, 0);
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return mode;
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}
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const struct drm_crtc_helper_funcs psb_intel_helper_funcs = {
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.dpms = gma_crtc_dpms,
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.mode_fixup = gma_crtc_mode_fixup,
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.mode_set = psb_intel_crtc_mode_set,
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.mode_set_base = gma_pipe_set_base,
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.prepare = gma_crtc_prepare,
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.commit = gma_crtc_commit,
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.disable = gma_crtc_disable,
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};
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const struct drm_crtc_funcs psb_intel_crtc_funcs = {
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.save = gma_crtc_save,
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.restore = gma_crtc_restore,
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.cursor_set = gma_crtc_cursor_set,
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.cursor_move = gma_crtc_cursor_move,
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.gamma_set = gma_crtc_gamma_set,
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.set_config = gma_crtc_set_config,
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.destroy = gma_crtc_destroy,
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};
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const struct gma_clock_funcs psb_clock_funcs = {
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.clock = psb_intel_clock,
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.limit = psb_intel_limit,
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.pll_is_valid = gma_pll_is_valid,
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};
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/*
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* Set the default value of cursor control and base register
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* to zero. This is a workaround for h/w defect on Oaktrail
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*/
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static void psb_intel_cursor_init(struct drm_device *dev,
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struct gma_crtc *gma_crtc)
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{
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struct drm_psb_private *dev_priv = dev->dev_private;
|
|
u32 control[3] = { CURACNTR, CURBCNTR, CURCCNTR };
|
|
u32 base[3] = { CURABASE, CURBBASE, CURCBASE };
|
|
struct gtt_range *cursor_gt;
|
|
|
|
if (dev_priv->ops->cursor_needs_phys) {
|
|
/* Allocate 4 pages of stolen mem for a hardware cursor. That
|
|
* is enough for the 64 x 64 ARGB cursors we support.
|
|
*/
|
|
cursor_gt = psb_gtt_alloc_range(dev, 4 * PAGE_SIZE, "cursor", 1);
|
|
if (!cursor_gt) {
|
|
gma_crtc->cursor_gt = NULL;
|
|
goto out;
|
|
}
|
|
gma_crtc->cursor_gt = cursor_gt;
|
|
gma_crtc->cursor_addr = dev_priv->stolen_base +
|
|
cursor_gt->offset;
|
|
} else {
|
|
gma_crtc->cursor_gt = NULL;
|
|
}
|
|
|
|
out:
|
|
REG_WRITE(control[gma_crtc->pipe], 0);
|
|
REG_WRITE(base[gma_crtc->pipe], 0);
|
|
}
|
|
|
|
void psb_intel_crtc_init(struct drm_device *dev, int pipe,
|
|
struct psb_intel_mode_device *mode_dev)
|
|
{
|
|
struct drm_psb_private *dev_priv = dev->dev_private;
|
|
struct gma_crtc *gma_crtc;
|
|
int i;
|
|
uint16_t *r_base, *g_base, *b_base;
|
|
|
|
/* We allocate a extra array of drm_connector pointers
|
|
* for fbdev after the crtc */
|
|
gma_crtc = kzalloc(sizeof(struct gma_crtc) +
|
|
(INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)),
|
|
GFP_KERNEL);
|
|
if (gma_crtc == NULL)
|
|
return;
|
|
|
|
gma_crtc->crtc_state =
|
|
kzalloc(sizeof(struct psb_intel_crtc_state), GFP_KERNEL);
|
|
if (!gma_crtc->crtc_state) {
|
|
dev_err(dev->dev, "Crtc state error: No memory\n");
|
|
kfree(gma_crtc);
|
|
return;
|
|
}
|
|
|
|
/* Set the CRTC operations from the chip specific data */
|
|
drm_crtc_init(dev, &gma_crtc->base, dev_priv->ops->crtc_funcs);
|
|
|
|
/* Set the CRTC clock functions from chip specific data */
|
|
gma_crtc->clock_funcs = dev_priv->ops->clock_funcs;
|
|
|
|
drm_mode_crtc_set_gamma_size(&gma_crtc->base, 256);
|
|
gma_crtc->pipe = pipe;
|
|
gma_crtc->plane = pipe;
|
|
|
|
r_base = gma_crtc->base.gamma_store;
|
|
g_base = r_base + 256;
|
|
b_base = g_base + 256;
|
|
for (i = 0; i < 256; i++) {
|
|
gma_crtc->lut_r[i] = i;
|
|
gma_crtc->lut_g[i] = i;
|
|
gma_crtc->lut_b[i] = i;
|
|
r_base[i] = i << 8;
|
|
g_base[i] = i << 8;
|
|
b_base[i] = i << 8;
|
|
|
|
gma_crtc->lut_adj[i] = 0;
|
|
}
|
|
|
|
gma_crtc->mode_dev = mode_dev;
|
|
gma_crtc->cursor_addr = 0;
|
|
|
|
drm_crtc_helper_add(&gma_crtc->base,
|
|
dev_priv->ops->crtc_helper);
|
|
|
|
/* Setup the array of drm_connector pointer array */
|
|
gma_crtc->mode_set.crtc = &gma_crtc->base;
|
|
BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
|
|
dev_priv->plane_to_crtc_mapping[gma_crtc->plane] != NULL);
|
|
dev_priv->plane_to_crtc_mapping[gma_crtc->plane] = &gma_crtc->base;
|
|
dev_priv->pipe_to_crtc_mapping[gma_crtc->pipe] = &gma_crtc->base;
|
|
gma_crtc->mode_set.connectors = (struct drm_connector **)(gma_crtc + 1);
|
|
gma_crtc->mode_set.num_connectors = 0;
|
|
psb_intel_cursor_init(dev, gma_crtc);
|
|
|
|
/* Set to true so that the pipe is forced off on initial config. */
|
|
gma_crtc->active = true;
|
|
}
|
|
|
|
int psb_intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv)
|
|
{
|
|
struct drm_psb_private *dev_priv = dev->dev_private;
|
|
struct drm_psb_get_pipe_from_crtc_id_arg *pipe_from_crtc_id = data;
|
|
struct drm_mode_object *drmmode_obj;
|
|
struct gma_crtc *crtc;
|
|
|
|
if (!dev_priv) {
|
|
dev_err(dev->dev, "called with no initialization\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
|
|
DRM_MODE_OBJECT_CRTC);
|
|
|
|
if (!drmmode_obj) {
|
|
dev_err(dev->dev, "no such CRTC id\n");
|
|
return -ENOENT;
|
|
}
|
|
|
|
crtc = to_gma_crtc(obj_to_crtc(drmmode_obj));
|
|
pipe_from_crtc_id->pipe = crtc->pipe;
|
|
|
|
return 0;
|
|
}
|
|
|
|
struct drm_crtc *psb_intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
|
|
{
|
|
struct drm_crtc *crtc = NULL;
|
|
|
|
list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
|
|
struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
|
|
if (gma_crtc->pipe == pipe)
|
|
break;
|
|
}
|
|
return crtc;
|
|
}
|
|
|
|
int gma_connector_clones(struct drm_device *dev, int type_mask)
|
|
{
|
|
int index_mask = 0;
|
|
struct drm_connector *connector;
|
|
int entry = 0;
|
|
|
|
list_for_each_entry(connector, &dev->mode_config.connector_list,
|
|
head) {
|
|
struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
|
|
if (type_mask & (1 << gma_encoder->type))
|
|
index_mask |= (1 << entry);
|
|
entry++;
|
|
}
|
|
return index_mask;
|
|
}
|