dada25bd22
The HDMI block is basically the same between older SoC's with mdp4 display controller, and newer ones with mdp5. So mostly this consists of better abstracting out the different sets of regulators, clks, etc. In particular, for regulators and clks we can split it up by what is needed for hot plug detect to work, and what is needed to light up the display. Also, 8x74 has a new phy.. a very simple one, but split out into a different mmio space. And with mdp5, the irq is shared with mdp, so we don't directly register our own irq handler. Signed-off-by: Rob Clark <robdclark@gmail.com>
239 lines
7.4 KiB
C
239 lines
7.4 KiB
C
/*
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __MSM_DRV_H__
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#define __MSM_DRV_H__
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/cpufreq.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pm.h>
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#include <linux/pm_runtime.h>
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#include <linux/slab.h>
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#include <linux/list.h>
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#include <linux/iommu.h>
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#include <linux/types.h>
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#include <asm/sizes.h>
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#if defined(CONFIG_COMPILE_TEST) && !defined(CONFIG_ARCH_MSM)
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/* stubs we need for compile-test: */
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static inline struct device *msm_iommu_get_ctx(const char *ctx_name)
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{
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return NULL;
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}
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#endif
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#ifndef CONFIG_OF
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#include <mach/board.h>
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#include <mach/socinfo.h>
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#include <mach/iommu_domains.h>
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#endif
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#include <drm/drmP.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_fb_helper.h>
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#include <drm/msm_drm.h>
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struct msm_kms;
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struct msm_gpu;
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struct msm_mmu;
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#define NUM_DOMAINS 2 /* one for KMS, then one per gpu core (?) */
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struct msm_file_private {
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/* currently we don't do anything useful with this.. but when
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* per-context address spaces are supported we'd keep track of
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* the context's page-tables here.
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*/
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int dummy;
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};
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struct msm_drm_private {
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struct msm_kms *kms;
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/* when we have more than one 'msm_gpu' these need to be an array: */
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struct msm_gpu *gpu;
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struct msm_file_private *lastctx;
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struct drm_fb_helper *fbdev;
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uint32_t next_fence, completed_fence;
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wait_queue_head_t fence_event;
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/* list of GEM objects: */
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struct list_head inactive_list;
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struct workqueue_struct *wq;
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/* callbacks deferred until bo is inactive: */
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struct list_head fence_cbs;
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/* registered MMUs: */
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unsigned int num_mmus;
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struct msm_mmu *mmus[NUM_DOMAINS];
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unsigned int num_planes;
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struct drm_plane *planes[8];
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unsigned int num_crtcs;
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struct drm_crtc *crtcs[8];
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unsigned int num_encoders;
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struct drm_encoder *encoders[8];
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unsigned int num_bridges;
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struct drm_bridge *bridges[8];
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unsigned int num_connectors;
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struct drm_connector *connectors[8];
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/* VRAM carveout, used when no IOMMU: */
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struct {
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unsigned long size;
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dma_addr_t paddr;
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/* NOTE: mm managed at the page level, size is in # of pages
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* and position mm_node->start is in # of pages:
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*/
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struct drm_mm mm;
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} vram;
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};
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struct msm_format {
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uint32_t pixel_format;
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};
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/* callback from wq once fence has passed: */
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struct msm_fence_cb {
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struct work_struct work;
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uint32_t fence;
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void (*func)(struct msm_fence_cb *cb);
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};
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void __msm_fence_worker(struct work_struct *work);
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#define INIT_FENCE_CB(_cb, _func) do { \
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INIT_WORK(&(_cb)->work, __msm_fence_worker); \
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(_cb)->func = _func; \
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} while (0)
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int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu);
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int msm_wait_fence_interruptable(struct drm_device *dev, uint32_t fence,
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struct timespec *timeout);
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void msm_update_fence(struct drm_device *dev, uint32_t fence);
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int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
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struct drm_file *file);
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int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma);
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int msm_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
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uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj);
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int msm_gem_get_iova_locked(struct drm_gem_object *obj, int id,
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uint32_t *iova);
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int msm_gem_get_iova(struct drm_gem_object *obj, int id, uint32_t *iova);
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struct page **msm_gem_get_pages(struct drm_gem_object *obj);
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void msm_gem_put_pages(struct drm_gem_object *obj);
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void msm_gem_put_iova(struct drm_gem_object *obj, int id);
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int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
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struct drm_mode_create_dumb *args);
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int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev,
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uint32_t handle, uint64_t *offset);
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struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj);
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void *msm_gem_prime_vmap(struct drm_gem_object *obj);
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void msm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
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struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev,
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size_t size, struct sg_table *sg);
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int msm_gem_prime_pin(struct drm_gem_object *obj);
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void msm_gem_prime_unpin(struct drm_gem_object *obj);
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void *msm_gem_vaddr_locked(struct drm_gem_object *obj);
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void *msm_gem_vaddr(struct drm_gem_object *obj);
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int msm_gem_queue_inactive_cb(struct drm_gem_object *obj,
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struct msm_fence_cb *cb);
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void msm_gem_move_to_active(struct drm_gem_object *obj,
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struct msm_gpu *gpu, bool write, uint32_t fence);
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void msm_gem_move_to_inactive(struct drm_gem_object *obj);
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int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op,
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struct timespec *timeout);
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int msm_gem_cpu_fini(struct drm_gem_object *obj);
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void msm_gem_free_object(struct drm_gem_object *obj);
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int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file,
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uint32_t size, uint32_t flags, uint32_t *handle);
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struct drm_gem_object *msm_gem_new(struct drm_device *dev,
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uint32_t size, uint32_t flags);
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struct drm_gem_object *msm_gem_import(struct drm_device *dev,
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uint32_t size, struct sg_table *sgt);
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struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane);
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const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb);
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struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev,
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struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos);
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struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,
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struct drm_file *file, struct drm_mode_fb_cmd2 *mode_cmd);
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struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev);
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struct hdmi;
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struct hdmi *hdmi_init(struct drm_device *dev, struct drm_encoder *encoder);
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irqreturn_t hdmi_irq(int irq, void *dev_id);
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void __init hdmi_register(void);
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void __exit hdmi_unregister(void);
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#ifdef CONFIG_DEBUG_FS
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void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m);
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void msm_gem_describe_objects(struct list_head *list, struct seq_file *m);
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void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m);
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#endif
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void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
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const char *dbgname);
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void msm_writel(u32 data, void __iomem *addr);
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u32 msm_readl(const void __iomem *addr);
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#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
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#define VERB(fmt, ...) if (0) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
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static inline bool fence_completed(struct drm_device *dev, uint32_t fence)
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{
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struct msm_drm_private *priv = dev->dev_private;
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return priv->completed_fence >= fence;
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}
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static inline int align_pitch(int width, int bpp)
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{
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int bytespp = (bpp + 7) / 8;
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/* adreno needs pitch aligned to 32 pixels: */
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return bytespp * ALIGN(width, 32);
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}
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/* for the generated headers: */
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#define INVALID_IDX(idx) ({BUG(); 0;})
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#define fui(x) ({BUG(); 0;})
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#define util_float_to_half(x) ({BUG(); 0;})
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#define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)
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/* for conditionally setting boolean flag(s): */
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#define COND(bool, val) ((bool) ? (val) : 0)
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#endif /* __MSM_DRV_H__ */
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