![Mihail Atanassov](/assets/img/avatar_default.png)
Internally Mali DP uses an RGB pipeline so video layers that support YUV input buffers need to convert the input data to RGB. The YUV buffers can have various encodings and this patch introduces support for BT.601, BT.709 and BT.2020 encodings, both limited and full ranges. This patch adds support for specifying the color encoding of the input buffers for the planes that are backed by the video layers and programs the YUV2RGB coefficients into hardware based on the selected encoding. Signed-off-by: Mihail Atanassov <mihail.atanassov@arm.com> [updated to use standard properties] Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
931 lines
31 KiB
C
931 lines
31 KiB
C
/*
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* (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
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* Author: Liviu Dudau <Liviu.Dudau@arm.com>
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*
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* This program is free software and is provided to you under the terms of the
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* GNU General Public License version 2 as published by the Free Software
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* Foundation, and any use by you of this program is subject to the terms
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* of such GNU licence.
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*
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* ARM Mali DP500/DP550/DP650 hardware manipulation routines. This is where
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* the difference between various versions of the hardware is being dealt with
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* in an attempt to provide to the rest of the driver code a unified view
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*/
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#include <linux/clk.h>
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#include <linux/types.h>
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#include <linux/io.h>
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#include <drm/drmP.h>
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#include <video/videomode.h>
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#include <video/display_timing.h>
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#include "malidp_drv.h"
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#include "malidp_hw.h"
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static const struct malidp_format_id malidp500_de_formats[] = {
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/* fourcc, layers supporting the format, internal id */
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{ DRM_FORMAT_ARGB2101010, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 0 },
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{ DRM_FORMAT_ABGR2101010, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 1 },
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{ DRM_FORMAT_ARGB8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 2 },
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{ DRM_FORMAT_ABGR8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 3 },
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{ DRM_FORMAT_XRGB8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 4 },
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{ DRM_FORMAT_XBGR8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 5 },
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{ DRM_FORMAT_RGB888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 6 },
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{ DRM_FORMAT_BGR888, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 7 },
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{ DRM_FORMAT_RGBA5551, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 8 },
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{ DRM_FORMAT_ABGR1555, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 9 },
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{ DRM_FORMAT_RGB565, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 10 },
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{ DRM_FORMAT_BGR565, DE_VIDEO1 | DE_GRAPHICS1 | DE_GRAPHICS2, 11 },
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{ DRM_FORMAT_UYVY, DE_VIDEO1, 12 },
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{ DRM_FORMAT_YUYV, DE_VIDEO1, 13 },
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{ DRM_FORMAT_NV12, DE_VIDEO1, 14 },
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{ DRM_FORMAT_YUV420, DE_VIDEO1, 15 },
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};
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#define MALIDP_ID(__group, __format) \
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((((__group) & 0x7) << 3) | ((__format) & 0x7))
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#define MALIDP_COMMON_FORMATS \
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/* fourcc, layers supporting the format, internal id */ \
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{ DRM_FORMAT_ARGB2101010, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(0, 0) }, \
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{ DRM_FORMAT_ABGR2101010, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(0, 1) }, \
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{ DRM_FORMAT_RGBA1010102, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(0, 2) }, \
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{ DRM_FORMAT_BGRA1010102, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(0, 3) }, \
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{ DRM_FORMAT_ARGB8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(1, 0) }, \
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{ DRM_FORMAT_ABGR8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(1, 1) }, \
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{ DRM_FORMAT_RGBA8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(1, 2) }, \
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{ DRM_FORMAT_BGRA8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(1, 3) }, \
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{ DRM_FORMAT_XRGB8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(2, 0) }, \
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{ DRM_FORMAT_XBGR8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(2, 1) }, \
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{ DRM_FORMAT_RGBX8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(2, 2) }, \
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{ DRM_FORMAT_BGRX8888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2 | DE_SMART, MALIDP_ID(2, 3) }, \
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{ DRM_FORMAT_RGB888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(3, 0) }, \
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{ DRM_FORMAT_BGR888, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(3, 1) }, \
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{ DRM_FORMAT_RGBA5551, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(4, 0) }, \
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{ DRM_FORMAT_ABGR1555, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(4, 1) }, \
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{ DRM_FORMAT_RGB565, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(4, 2) }, \
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{ DRM_FORMAT_BGR565, DE_VIDEO1 | DE_GRAPHICS1 | DE_VIDEO2, MALIDP_ID(4, 3) }, \
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{ DRM_FORMAT_YUYV, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 2) }, \
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{ DRM_FORMAT_UYVY, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 3) }, \
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{ DRM_FORMAT_NV12, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 6) }, \
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{ DRM_FORMAT_YUV420, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 7) }
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static const struct malidp_format_id malidp550_de_formats[] = {
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MALIDP_COMMON_FORMATS,
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};
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static const struct malidp_layer malidp500_layers[] = {
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{ DE_VIDEO1, MALIDP500_DE_LV_BASE, MALIDP500_DE_LV_PTR_BASE, MALIDP_DE_LV_STRIDE0, MALIDP500_LV_YUV2RGB },
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{ DE_GRAPHICS1, MALIDP500_DE_LG1_BASE, MALIDP500_DE_LG1_PTR_BASE, MALIDP_DE_LG_STRIDE, 0 },
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{ DE_GRAPHICS2, MALIDP500_DE_LG2_BASE, MALIDP500_DE_LG2_PTR_BASE, MALIDP_DE_LG_STRIDE, 0 },
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};
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static const struct malidp_layer malidp550_layers[] = {
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{ DE_VIDEO1, MALIDP550_DE_LV1_BASE, MALIDP550_DE_LV1_PTR_BASE, MALIDP_DE_LV_STRIDE0, MALIDP550_LV_YUV2RGB },
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{ DE_GRAPHICS1, MALIDP550_DE_LG_BASE, MALIDP550_DE_LG_PTR_BASE, MALIDP_DE_LG_STRIDE, 0 },
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{ DE_VIDEO2, MALIDP550_DE_LV2_BASE, MALIDP550_DE_LV2_PTR_BASE, MALIDP_DE_LV_STRIDE0, MALIDP550_LV_YUV2RGB },
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{ DE_SMART, MALIDP550_DE_LS_BASE, MALIDP550_DE_LS_PTR_BASE, MALIDP550_DE_LS_R1_STRIDE, 0 },
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};
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#define SE_N_SCALING_COEFFS 96
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static const u16 dp500_se_scaling_coeffs[][SE_N_SCALING_COEFFS] = {
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[MALIDP_UPSCALING_COEFFS - 1] = {
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0x0000, 0x0001, 0x0007, 0x0011, 0x001e, 0x002e, 0x003f, 0x0052,
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0x0064, 0x0073, 0x007d, 0x0080, 0x007a, 0x006c, 0x0053, 0x002f,
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0x0000, 0x3fc6, 0x3f83, 0x3f39, 0x3eea, 0x3e9b, 0x3e4f, 0x3e0a,
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0x3dd4, 0x3db0, 0x3da2, 0x3db1, 0x3dde, 0x3e2f, 0x3ea5, 0x3f40,
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0x0000, 0x00e5, 0x01ee, 0x0315, 0x0456, 0x05aa, 0x0709, 0x086c,
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0x09c9, 0x0b15, 0x0c4a, 0x0d5d, 0x0e4a, 0x0f06, 0x0f91, 0x0fe5,
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0x1000, 0x0fe5, 0x0f91, 0x0f06, 0x0e4a, 0x0d5d, 0x0c4a, 0x0b15,
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0x09c9, 0x086c, 0x0709, 0x05aa, 0x0456, 0x0315, 0x01ee, 0x00e5,
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0x0000, 0x3f40, 0x3ea5, 0x3e2f, 0x3dde, 0x3db1, 0x3da2, 0x3db0,
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0x3dd4, 0x3e0a, 0x3e4f, 0x3e9b, 0x3eea, 0x3f39, 0x3f83, 0x3fc6,
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0x0000, 0x002f, 0x0053, 0x006c, 0x007a, 0x0080, 0x007d, 0x0073,
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0x0064, 0x0052, 0x003f, 0x002e, 0x001e, 0x0011, 0x0007, 0x0001
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},
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[MALIDP_DOWNSCALING_1_5_COEFFS - 1] = {
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0x0059, 0x004f, 0x0041, 0x002e, 0x0016, 0x3ffb, 0x3fd9, 0x3fb4,
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0x3f8c, 0x3f62, 0x3f36, 0x3f09, 0x3edd, 0x3eb3, 0x3e8d, 0x3e6c,
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0x3e52, 0x3e3f, 0x3e35, 0x3e37, 0x3e46, 0x3e61, 0x3e8c, 0x3ec5,
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0x3f0f, 0x3f68, 0x3fd1, 0x004a, 0x00d3, 0x0169, 0x020b, 0x02b8,
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0x036e, 0x042d, 0x04f2, 0x05b9, 0x0681, 0x0745, 0x0803, 0x08ba,
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0x0965, 0x0a03, 0x0a91, 0x0b0d, 0x0b75, 0x0bc6, 0x0c00, 0x0c20,
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0x0c28, 0x0c20, 0x0c00, 0x0bc6, 0x0b75, 0x0b0d, 0x0a91, 0x0a03,
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0x0965, 0x08ba, 0x0803, 0x0745, 0x0681, 0x05b9, 0x04f2, 0x042d,
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0x036e, 0x02b8, 0x020b, 0x0169, 0x00d3, 0x004a, 0x3fd1, 0x3f68,
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0x3f0f, 0x3ec5, 0x3e8c, 0x3e61, 0x3e46, 0x3e37, 0x3e35, 0x3e3f,
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0x3e52, 0x3e6c, 0x3e8d, 0x3eb3, 0x3edd, 0x3f09, 0x3f36, 0x3f62,
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0x3f8c, 0x3fb4, 0x3fd9, 0x3ffb, 0x0016, 0x002e, 0x0041, 0x004f
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},
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[MALIDP_DOWNSCALING_2_COEFFS - 1] = {
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0x3f19, 0x3f03, 0x3ef0, 0x3edf, 0x3ed0, 0x3ec5, 0x3ebd, 0x3eb9,
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0x3eb9, 0x3ebf, 0x3eca, 0x3ed9, 0x3eef, 0x3f0a, 0x3f2c, 0x3f52,
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0x3f7f, 0x3fb0, 0x3fe8, 0x0026, 0x006a, 0x00b4, 0x0103, 0x0158,
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0x01b1, 0x020d, 0x026c, 0x02cd, 0x032f, 0x0392, 0x03f4, 0x0455,
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0x04b4, 0x051e, 0x0585, 0x05eb, 0x064c, 0x06a8, 0x06fe, 0x074e,
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0x0796, 0x07d5, 0x080c, 0x0839, 0x085c, 0x0875, 0x0882, 0x0887,
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0x0881, 0x0887, 0x0882, 0x0875, 0x085c, 0x0839, 0x080c, 0x07d5,
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0x0796, 0x074e, 0x06fe, 0x06a8, 0x064c, 0x05eb, 0x0585, 0x051e,
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0x04b4, 0x0455, 0x03f4, 0x0392, 0x032f, 0x02cd, 0x026c, 0x020d,
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0x01b1, 0x0158, 0x0103, 0x00b4, 0x006a, 0x0026, 0x3fe8, 0x3fb0,
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0x3f7f, 0x3f52, 0x3f2c, 0x3f0a, 0x3eef, 0x3ed9, 0x3eca, 0x3ebf,
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0x3eb9, 0x3eb9, 0x3ebd, 0x3ec5, 0x3ed0, 0x3edf, 0x3ef0, 0x3f03
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},
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[MALIDP_DOWNSCALING_2_75_COEFFS - 1] = {
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0x3f51, 0x3f60, 0x3f71, 0x3f84, 0x3f98, 0x3faf, 0x3fc8, 0x3fe3,
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0x0000, 0x001f, 0x0040, 0x0064, 0x008a, 0x00b1, 0x00da, 0x0106,
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0x0133, 0x0160, 0x018e, 0x01bd, 0x01ec, 0x021d, 0x024e, 0x0280,
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0x02b2, 0x02e4, 0x0317, 0x0349, 0x037c, 0x03ad, 0x03df, 0x0410,
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0x0440, 0x0468, 0x048f, 0x04b3, 0x04d6, 0x04f8, 0x0516, 0x0533,
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0x054e, 0x0566, 0x057c, 0x0590, 0x05a0, 0x05ae, 0x05ba, 0x05c3,
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0x05c9, 0x05c3, 0x05ba, 0x05ae, 0x05a0, 0x0590, 0x057c, 0x0566,
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0x054e, 0x0533, 0x0516, 0x04f8, 0x04d6, 0x04b3, 0x048f, 0x0468,
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0x0440, 0x0410, 0x03df, 0x03ad, 0x037c, 0x0349, 0x0317, 0x02e4,
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0x02b2, 0x0280, 0x024e, 0x021d, 0x01ec, 0x01bd, 0x018e, 0x0160,
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0x0133, 0x0106, 0x00da, 0x00b1, 0x008a, 0x0064, 0x0040, 0x001f,
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0x0000, 0x3fe3, 0x3fc8, 0x3faf, 0x3f98, 0x3f84, 0x3f71, 0x3f60
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},
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[MALIDP_DOWNSCALING_4_COEFFS - 1] = {
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0x0094, 0x00a9, 0x00be, 0x00d4, 0x00ea, 0x0101, 0x0118, 0x012f,
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0x0148, 0x0160, 0x017a, 0x0193, 0x01ae, 0x01c8, 0x01e4, 0x01ff,
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0x021c, 0x0233, 0x024a, 0x0261, 0x0278, 0x028f, 0x02a6, 0x02bd,
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0x02d4, 0x02eb, 0x0302, 0x0319, 0x032f, 0x0346, 0x035d, 0x0374,
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0x038a, 0x0397, 0x03a3, 0x03af, 0x03bb, 0x03c6, 0x03d1, 0x03db,
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0x03e4, 0x03ed, 0x03f6, 0x03fe, 0x0406, 0x040d, 0x0414, 0x041a,
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0x0420, 0x041a, 0x0414, 0x040d, 0x0406, 0x03fe, 0x03f6, 0x03ed,
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0x03e4, 0x03db, 0x03d1, 0x03c6, 0x03bb, 0x03af, 0x03a3, 0x0397,
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0x038a, 0x0374, 0x035d, 0x0346, 0x032f, 0x0319, 0x0302, 0x02eb,
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0x02d4, 0x02bd, 0x02a6, 0x028f, 0x0278, 0x0261, 0x024a, 0x0233,
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0x021c, 0x01ff, 0x01e4, 0x01c8, 0x01ae, 0x0193, 0x017a, 0x0160,
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0x0148, 0x012f, 0x0118, 0x0101, 0x00ea, 0x00d4, 0x00be, 0x00a9
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},
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};
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#define MALIDP_DE_DEFAULT_PREFETCH_START 5
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static int malidp500_query_hw(struct malidp_hw_device *hwdev)
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{
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u32 conf = malidp_hw_read(hwdev, MALIDP500_CONFIG_ID);
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/* bit 4 of the CONFIG_ID register holds the line size multiplier */
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u8 ln_size_mult = conf & 0x10 ? 2 : 1;
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hwdev->min_line_size = 2;
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hwdev->max_line_size = SZ_2K * ln_size_mult;
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hwdev->rotation_memory[0] = SZ_1K * 64 * ln_size_mult;
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hwdev->rotation_memory[1] = 0; /* no second rotation memory bank */
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return 0;
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}
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static void malidp500_enter_config_mode(struct malidp_hw_device *hwdev)
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{
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u32 status, count = 100;
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malidp_hw_setbits(hwdev, MALIDP500_DC_CONFIG_REQ, MALIDP500_DC_CONTROL);
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while (count) {
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status = malidp_hw_read(hwdev, hwdev->hw->map.dc_base + MALIDP_REG_STATUS);
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if ((status & MALIDP500_DC_CONFIG_REQ) == MALIDP500_DC_CONFIG_REQ)
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break;
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/*
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* entering config mode can take as long as the rendering
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* of a full frame, hence the long sleep here
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*/
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usleep_range(1000, 10000);
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count--;
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}
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WARN(count == 0, "timeout while entering config mode");
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}
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static void malidp500_leave_config_mode(struct malidp_hw_device *hwdev)
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{
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u32 status, count = 100;
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malidp_hw_clearbits(hwdev, MALIDP_CFG_VALID, MALIDP500_CONFIG_VALID);
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malidp_hw_clearbits(hwdev, MALIDP500_DC_CONFIG_REQ, MALIDP500_DC_CONTROL);
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while (count) {
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status = malidp_hw_read(hwdev, hwdev->hw->map.dc_base + MALIDP_REG_STATUS);
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if ((status & MALIDP500_DC_CONFIG_REQ) == 0)
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break;
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usleep_range(100, 1000);
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count--;
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}
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WARN(count == 0, "timeout while leaving config mode");
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}
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static bool malidp500_in_config_mode(struct malidp_hw_device *hwdev)
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{
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u32 status;
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status = malidp_hw_read(hwdev, hwdev->hw->map.dc_base + MALIDP_REG_STATUS);
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if ((status & MALIDP500_DC_CONFIG_REQ) == MALIDP500_DC_CONFIG_REQ)
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return true;
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return false;
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}
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static void malidp500_set_config_valid(struct malidp_hw_device *hwdev)
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{
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malidp_hw_setbits(hwdev, MALIDP_CFG_VALID, MALIDP500_CONFIG_VALID);
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}
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static void malidp500_modeset(struct malidp_hw_device *hwdev, struct videomode *mode)
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{
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u32 val = 0;
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malidp_hw_clearbits(hwdev, MALIDP500_DC_CLEAR_MASK, MALIDP500_DC_CONTROL);
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if (mode->flags & DISPLAY_FLAGS_HSYNC_HIGH)
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val |= MALIDP500_HSYNCPOL;
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if (mode->flags & DISPLAY_FLAGS_VSYNC_HIGH)
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val |= MALIDP500_VSYNCPOL;
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val |= MALIDP_DE_DEFAULT_PREFETCH_START;
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malidp_hw_setbits(hwdev, val, MALIDP500_DC_CONTROL);
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/*
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* Mali-DP500 encodes the background color like this:
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* - red @ MALIDP500_BGND_COLOR[12:0]
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* - green @ MALIDP500_BGND_COLOR[27:16]
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* - blue @ (MALIDP500_BGND_COLOR + 4)[12:0]
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*/
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val = ((MALIDP_BGND_COLOR_G & 0xfff) << 16) |
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(MALIDP_BGND_COLOR_R & 0xfff);
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malidp_hw_write(hwdev, val, MALIDP500_BGND_COLOR);
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malidp_hw_write(hwdev, MALIDP_BGND_COLOR_B, MALIDP500_BGND_COLOR + 4);
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val = MALIDP_DE_H_FRONTPORCH(mode->hfront_porch) |
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MALIDP_DE_H_BACKPORCH(mode->hback_porch);
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malidp_hw_write(hwdev, val, MALIDP500_TIMINGS_BASE + MALIDP_DE_H_TIMINGS);
|
|
|
|
val = MALIDP500_DE_V_FRONTPORCH(mode->vfront_porch) |
|
|
MALIDP_DE_V_BACKPORCH(mode->vback_porch);
|
|
malidp_hw_write(hwdev, val, MALIDP500_TIMINGS_BASE + MALIDP_DE_V_TIMINGS);
|
|
|
|
val = MALIDP_DE_H_SYNCWIDTH(mode->hsync_len) |
|
|
MALIDP_DE_V_SYNCWIDTH(mode->vsync_len);
|
|
malidp_hw_write(hwdev, val, MALIDP500_TIMINGS_BASE + MALIDP_DE_SYNC_WIDTH);
|
|
|
|
val = MALIDP_DE_H_ACTIVE(mode->hactive) | MALIDP_DE_V_ACTIVE(mode->vactive);
|
|
malidp_hw_write(hwdev, val, MALIDP500_TIMINGS_BASE + MALIDP_DE_HV_ACTIVE);
|
|
|
|
if (mode->flags & DISPLAY_FLAGS_INTERLACED)
|
|
malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC);
|
|
else
|
|
malidp_hw_clearbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC);
|
|
}
|
|
|
|
static int malidp500_rotmem_required(struct malidp_hw_device *hwdev, u16 w, u16 h, u32 fmt)
|
|
{
|
|
/* RGB888 or BGR888 can't be rotated */
|
|
if ((fmt == DRM_FORMAT_RGB888) || (fmt == DRM_FORMAT_BGR888))
|
|
return -EINVAL;
|
|
|
|
/*
|
|
* Each layer needs enough rotation memory to fit 8 lines
|
|
* worth of pixel data. Required size is then:
|
|
* size = rotated_width * (bpp / 8) * 8;
|
|
*/
|
|
return w * drm_format_plane_cpp(fmt, 0) * 8;
|
|
}
|
|
|
|
static void malidp500_se_write_pp_coefftab(struct malidp_hw_device *hwdev,
|
|
u32 direction,
|
|
u16 addr,
|
|
u8 coeffs_id)
|
|
{
|
|
int i;
|
|
u16 scaling_control = MALIDP500_SE_CONTROL + MALIDP_SE_SCALING_CONTROL;
|
|
|
|
malidp_hw_write(hwdev,
|
|
direction | (addr & MALIDP_SE_COEFFTAB_ADDR_MASK),
|
|
scaling_control + MALIDP_SE_COEFFTAB_ADDR);
|
|
for (i = 0; i < ARRAY_SIZE(dp500_se_scaling_coeffs); ++i)
|
|
malidp_hw_write(hwdev, MALIDP_SE_SET_COEFFTAB_DATA(
|
|
dp500_se_scaling_coeffs[coeffs_id][i]),
|
|
scaling_control + MALIDP_SE_COEFFTAB_DATA);
|
|
}
|
|
|
|
static int malidp500_se_set_scaling_coeffs(struct malidp_hw_device *hwdev,
|
|
struct malidp_se_config *se_config,
|
|
struct malidp_se_config *old_config)
|
|
{
|
|
/* Get array indices into dp500_se_scaling_coeffs. */
|
|
u8 h = (u8)se_config->hcoeff - 1;
|
|
u8 v = (u8)se_config->vcoeff - 1;
|
|
|
|
if (WARN_ON(h >= ARRAY_SIZE(dp500_se_scaling_coeffs) ||
|
|
v >= ARRAY_SIZE(dp500_se_scaling_coeffs)))
|
|
return -EINVAL;
|
|
|
|
if ((h == v) && (se_config->hcoeff != old_config->hcoeff ||
|
|
se_config->vcoeff != old_config->vcoeff)) {
|
|
malidp500_se_write_pp_coefftab(hwdev,
|
|
(MALIDP_SE_V_COEFFTAB |
|
|
MALIDP_SE_H_COEFFTAB),
|
|
0, v);
|
|
} else {
|
|
if (se_config->vcoeff != old_config->vcoeff)
|
|
malidp500_se_write_pp_coefftab(hwdev,
|
|
MALIDP_SE_V_COEFFTAB,
|
|
0, v);
|
|
if (se_config->hcoeff != old_config->hcoeff)
|
|
malidp500_se_write_pp_coefftab(hwdev,
|
|
MALIDP_SE_H_COEFFTAB,
|
|
0, h);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static long malidp500_se_calc_mclk(struct malidp_hw_device *hwdev,
|
|
struct malidp_se_config *se_config,
|
|
struct videomode *vm)
|
|
{
|
|
unsigned long mclk;
|
|
unsigned long pxlclk = vm->pixelclock; /* Hz */
|
|
unsigned long htotal = vm->hactive + vm->hfront_porch +
|
|
vm->hback_porch + vm->hsync_len;
|
|
unsigned long input_size = se_config->input_w * se_config->input_h;
|
|
unsigned long a = 10;
|
|
long ret;
|
|
|
|
/*
|
|
* mclk = max(a, 1.5) * pxlclk
|
|
*
|
|
* To avoid float calculaiton, using 15 instead of 1.5 and div by
|
|
* 10 to get mclk.
|
|
*/
|
|
if (se_config->scale_enable) {
|
|
a = 15 * input_size / (htotal * se_config->output_h);
|
|
if (a < 15)
|
|
a = 15;
|
|
}
|
|
mclk = a * pxlclk / 10;
|
|
ret = clk_get_rate(hwdev->mclk);
|
|
if (ret < mclk) {
|
|
DRM_DEBUG_DRIVER("mclk requirement of %lu kHz can't be met.\n",
|
|
mclk / 1000);
|
|
return -EINVAL;
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static int malidp550_query_hw(struct malidp_hw_device *hwdev)
|
|
{
|
|
u32 conf = malidp_hw_read(hwdev, MALIDP550_CONFIG_ID);
|
|
u8 ln_size = (conf >> 4) & 0x3, rsize;
|
|
|
|
hwdev->min_line_size = 2;
|
|
|
|
switch (ln_size) {
|
|
case 0:
|
|
hwdev->max_line_size = SZ_2K;
|
|
/* two banks of 64KB for rotation memory */
|
|
rsize = 64;
|
|
break;
|
|
case 1:
|
|
hwdev->max_line_size = SZ_4K;
|
|
/* two banks of 128KB for rotation memory */
|
|
rsize = 128;
|
|
break;
|
|
case 2:
|
|
hwdev->max_line_size = 1280;
|
|
/* two banks of 40KB for rotation memory */
|
|
rsize = 40;
|
|
break;
|
|
case 3:
|
|
/* reserved value */
|
|
hwdev->max_line_size = 0;
|
|
return -EINVAL;
|
|
}
|
|
|
|
hwdev->rotation_memory[0] = hwdev->rotation_memory[1] = rsize * SZ_1K;
|
|
return 0;
|
|
}
|
|
|
|
static void malidp550_enter_config_mode(struct malidp_hw_device *hwdev)
|
|
{
|
|
u32 status, count = 100;
|
|
|
|
malidp_hw_setbits(hwdev, MALIDP550_DC_CONFIG_REQ, MALIDP550_DC_CONTROL);
|
|
while (count) {
|
|
status = malidp_hw_read(hwdev, hwdev->hw->map.dc_base + MALIDP_REG_STATUS);
|
|
if ((status & MALIDP550_DC_CONFIG_REQ) == MALIDP550_DC_CONFIG_REQ)
|
|
break;
|
|
/*
|
|
* entering config mode can take as long as the rendering
|
|
* of a full frame, hence the long sleep here
|
|
*/
|
|
usleep_range(1000, 10000);
|
|
count--;
|
|
}
|
|
WARN(count == 0, "timeout while entering config mode");
|
|
}
|
|
|
|
static void malidp550_leave_config_mode(struct malidp_hw_device *hwdev)
|
|
{
|
|
u32 status, count = 100;
|
|
|
|
malidp_hw_clearbits(hwdev, MALIDP_CFG_VALID, MALIDP550_CONFIG_VALID);
|
|
malidp_hw_clearbits(hwdev, MALIDP550_DC_CONFIG_REQ, MALIDP550_DC_CONTROL);
|
|
while (count) {
|
|
status = malidp_hw_read(hwdev, hwdev->hw->map.dc_base + MALIDP_REG_STATUS);
|
|
if ((status & MALIDP550_DC_CONFIG_REQ) == 0)
|
|
break;
|
|
usleep_range(100, 1000);
|
|
count--;
|
|
}
|
|
WARN(count == 0, "timeout while leaving config mode");
|
|
}
|
|
|
|
static bool malidp550_in_config_mode(struct malidp_hw_device *hwdev)
|
|
{
|
|
u32 status;
|
|
|
|
status = malidp_hw_read(hwdev, hwdev->hw->map.dc_base + MALIDP_REG_STATUS);
|
|
if ((status & MALIDP550_DC_CONFIG_REQ) == MALIDP550_DC_CONFIG_REQ)
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
static void malidp550_set_config_valid(struct malidp_hw_device *hwdev)
|
|
{
|
|
malidp_hw_setbits(hwdev, MALIDP_CFG_VALID, MALIDP550_CONFIG_VALID);
|
|
}
|
|
|
|
static void malidp550_modeset(struct malidp_hw_device *hwdev, struct videomode *mode)
|
|
{
|
|
u32 val = MALIDP_DE_DEFAULT_PREFETCH_START;
|
|
|
|
malidp_hw_write(hwdev, val, MALIDP550_DE_CONTROL);
|
|
/*
|
|
* Mali-DP550 and Mali-DP650 encode the background color like this:
|
|
* - red @ MALIDP550_DE_BGND_COLOR[23:16]
|
|
* - green @ MALIDP550_DE_BGND_COLOR[15:8]
|
|
* - blue @ MALIDP550_DE_BGND_COLOR[7:0]
|
|
*
|
|
* We need to truncate the least significant 4 bits from the default
|
|
* MALIDP_BGND_COLOR_x values
|
|
*/
|
|
val = (((MALIDP_BGND_COLOR_R >> 4) & 0xff) << 16) |
|
|
(((MALIDP_BGND_COLOR_G >> 4) & 0xff) << 8) |
|
|
((MALIDP_BGND_COLOR_B >> 4) & 0xff);
|
|
malidp_hw_write(hwdev, val, MALIDP550_DE_BGND_COLOR);
|
|
|
|
val = MALIDP_DE_H_FRONTPORCH(mode->hfront_porch) |
|
|
MALIDP_DE_H_BACKPORCH(mode->hback_porch);
|
|
malidp_hw_write(hwdev, val, MALIDP550_TIMINGS_BASE + MALIDP_DE_H_TIMINGS);
|
|
|
|
val = MALIDP550_DE_V_FRONTPORCH(mode->vfront_porch) |
|
|
MALIDP_DE_V_BACKPORCH(mode->vback_porch);
|
|
malidp_hw_write(hwdev, val, MALIDP550_TIMINGS_BASE + MALIDP_DE_V_TIMINGS);
|
|
|
|
val = MALIDP_DE_H_SYNCWIDTH(mode->hsync_len) |
|
|
MALIDP_DE_V_SYNCWIDTH(mode->vsync_len);
|
|
if (mode->flags & DISPLAY_FLAGS_HSYNC_HIGH)
|
|
val |= MALIDP550_HSYNCPOL;
|
|
if (mode->flags & DISPLAY_FLAGS_VSYNC_HIGH)
|
|
val |= MALIDP550_VSYNCPOL;
|
|
malidp_hw_write(hwdev, val, MALIDP550_TIMINGS_BASE + MALIDP_DE_SYNC_WIDTH);
|
|
|
|
val = MALIDP_DE_H_ACTIVE(mode->hactive) | MALIDP_DE_V_ACTIVE(mode->vactive);
|
|
malidp_hw_write(hwdev, val, MALIDP550_TIMINGS_BASE + MALIDP_DE_HV_ACTIVE);
|
|
|
|
if (mode->flags & DISPLAY_FLAGS_INTERLACED)
|
|
malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC);
|
|
else
|
|
malidp_hw_clearbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC);
|
|
}
|
|
|
|
static int malidp550_rotmem_required(struct malidp_hw_device *hwdev, u16 w, u16 h, u32 fmt)
|
|
{
|
|
u32 bytes_per_col;
|
|
|
|
/* raw RGB888 or BGR888 can't be rotated */
|
|
if ((fmt == DRM_FORMAT_RGB888) || (fmt == DRM_FORMAT_BGR888))
|
|
return -EINVAL;
|
|
|
|
switch (fmt) {
|
|
/* 8 lines at 4 bytes per pixel */
|
|
case DRM_FORMAT_ARGB2101010:
|
|
case DRM_FORMAT_ABGR2101010:
|
|
case DRM_FORMAT_RGBA1010102:
|
|
case DRM_FORMAT_BGRA1010102:
|
|
case DRM_FORMAT_ARGB8888:
|
|
case DRM_FORMAT_ABGR8888:
|
|
case DRM_FORMAT_RGBA8888:
|
|
case DRM_FORMAT_BGRA8888:
|
|
case DRM_FORMAT_XRGB8888:
|
|
case DRM_FORMAT_XBGR8888:
|
|
case DRM_FORMAT_RGBX8888:
|
|
case DRM_FORMAT_BGRX8888:
|
|
case DRM_FORMAT_RGB888:
|
|
case DRM_FORMAT_BGR888:
|
|
/* 16 lines at 2 bytes per pixel */
|
|
case DRM_FORMAT_RGBA5551:
|
|
case DRM_FORMAT_ABGR1555:
|
|
case DRM_FORMAT_RGB565:
|
|
case DRM_FORMAT_BGR565:
|
|
case DRM_FORMAT_UYVY:
|
|
case DRM_FORMAT_YUYV:
|
|
bytes_per_col = 32;
|
|
break;
|
|
/* 16 lines at 1.5 bytes per pixel */
|
|
case DRM_FORMAT_NV12:
|
|
case DRM_FORMAT_YUV420:
|
|
bytes_per_col = 24;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
return w * bytes_per_col;
|
|
}
|
|
|
|
static int malidp550_se_set_scaling_coeffs(struct malidp_hw_device *hwdev,
|
|
struct malidp_se_config *se_config,
|
|
struct malidp_se_config *old_config)
|
|
{
|
|
u32 mask = MALIDP550_SE_CTL_VCSEL(MALIDP550_SE_CTL_SEL_MASK) |
|
|
MALIDP550_SE_CTL_HCSEL(MALIDP550_SE_CTL_SEL_MASK);
|
|
u32 new_value = MALIDP550_SE_CTL_VCSEL(se_config->vcoeff) |
|
|
MALIDP550_SE_CTL_HCSEL(se_config->hcoeff);
|
|
|
|
malidp_hw_clearbits(hwdev, mask, MALIDP550_SE_CONTROL);
|
|
malidp_hw_setbits(hwdev, new_value, MALIDP550_SE_CONTROL);
|
|
return 0;
|
|
}
|
|
|
|
static long malidp550_se_calc_mclk(struct malidp_hw_device *hwdev,
|
|
struct malidp_se_config *se_config,
|
|
struct videomode *vm)
|
|
{
|
|
unsigned long mclk;
|
|
unsigned long pxlclk = vm->pixelclock;
|
|
unsigned long htotal = vm->hactive + vm->hfront_porch +
|
|
vm->hback_porch + vm->hsync_len;
|
|
unsigned long numerator = 1, denominator = 1;
|
|
long ret;
|
|
|
|
if (se_config->scale_enable) {
|
|
numerator = max(se_config->input_w, se_config->output_w) *
|
|
se_config->input_h;
|
|
numerator += se_config->output_w *
|
|
(se_config->output_h -
|
|
min(se_config->input_h, se_config->output_h));
|
|
denominator = (htotal - 2) * se_config->output_h;
|
|
}
|
|
|
|
/* mclk can't be slower than pxlclk. */
|
|
if (numerator < denominator)
|
|
numerator = denominator = 1;
|
|
mclk = (pxlclk * numerator) / denominator;
|
|
ret = clk_get_rate(hwdev->mclk);
|
|
if (ret < mclk) {
|
|
DRM_DEBUG_DRIVER("mclk requirement of %lu kHz can't be met.\n",
|
|
mclk / 1000);
|
|
return -EINVAL;
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static int malidp650_query_hw(struct malidp_hw_device *hwdev)
|
|
{
|
|
u32 conf = malidp_hw_read(hwdev, MALIDP550_CONFIG_ID);
|
|
u8 ln_size = (conf >> 4) & 0x3, rsize;
|
|
|
|
hwdev->min_line_size = 4;
|
|
|
|
switch (ln_size) {
|
|
case 0:
|
|
case 2:
|
|
/* reserved values */
|
|
hwdev->max_line_size = 0;
|
|
return -EINVAL;
|
|
case 1:
|
|
hwdev->max_line_size = SZ_4K;
|
|
/* two banks of 128KB for rotation memory */
|
|
rsize = 128;
|
|
break;
|
|
case 3:
|
|
hwdev->max_line_size = 2560;
|
|
/* two banks of 80KB for rotation memory */
|
|
rsize = 80;
|
|
}
|
|
|
|
hwdev->rotation_memory[0] = hwdev->rotation_memory[1] = rsize * SZ_1K;
|
|
return 0;
|
|
}
|
|
|
|
const struct malidp_hw malidp_device[MALIDP_MAX_DEVICES] = {
|
|
[MALIDP_500] = {
|
|
.map = {
|
|
.coeffs_base = MALIDP500_COEFFS_BASE,
|
|
.se_base = MALIDP500_SE_BASE,
|
|
.dc_base = MALIDP500_DC_BASE,
|
|
.out_depth_base = MALIDP500_OUTPUT_DEPTH,
|
|
.features = 0, /* no CLEARIRQ register */
|
|
.n_layers = ARRAY_SIZE(malidp500_layers),
|
|
.layers = malidp500_layers,
|
|
.de_irq_map = {
|
|
.irq_mask = MALIDP_DE_IRQ_UNDERRUN |
|
|
MALIDP500_DE_IRQ_AXI_ERR |
|
|
MALIDP500_DE_IRQ_VSYNC |
|
|
MALIDP500_DE_IRQ_GLOBAL,
|
|
.vsync_irq = MALIDP500_DE_IRQ_VSYNC,
|
|
},
|
|
.se_irq_map = {
|
|
.irq_mask = MALIDP500_SE_IRQ_CONF_MODE,
|
|
.vsync_irq = 0,
|
|
},
|
|
.dc_irq_map = {
|
|
.irq_mask = MALIDP500_DE_IRQ_CONF_VALID,
|
|
.vsync_irq = MALIDP500_DE_IRQ_CONF_VALID,
|
|
},
|
|
.pixel_formats = malidp500_de_formats,
|
|
.n_pixel_formats = ARRAY_SIZE(malidp500_de_formats),
|
|
.bus_align_bytes = 8,
|
|
},
|
|
.query_hw = malidp500_query_hw,
|
|
.enter_config_mode = malidp500_enter_config_mode,
|
|
.leave_config_mode = malidp500_leave_config_mode,
|
|
.in_config_mode = malidp500_in_config_mode,
|
|
.set_config_valid = malidp500_set_config_valid,
|
|
.modeset = malidp500_modeset,
|
|
.rotmem_required = malidp500_rotmem_required,
|
|
.se_set_scaling_coeffs = malidp500_se_set_scaling_coeffs,
|
|
.se_calc_mclk = malidp500_se_calc_mclk,
|
|
.features = MALIDP_DEVICE_LV_HAS_3_STRIDES,
|
|
},
|
|
[MALIDP_550] = {
|
|
.map = {
|
|
.coeffs_base = MALIDP550_COEFFS_BASE,
|
|
.se_base = MALIDP550_SE_BASE,
|
|
.dc_base = MALIDP550_DC_BASE,
|
|
.out_depth_base = MALIDP550_DE_OUTPUT_DEPTH,
|
|
.features = MALIDP_REGMAP_HAS_CLEARIRQ,
|
|
.n_layers = ARRAY_SIZE(malidp550_layers),
|
|
.layers = malidp550_layers,
|
|
.de_irq_map = {
|
|
.irq_mask = MALIDP_DE_IRQ_UNDERRUN |
|
|
MALIDP550_DE_IRQ_VSYNC,
|
|
.vsync_irq = MALIDP550_DE_IRQ_VSYNC,
|
|
},
|
|
.se_irq_map = {
|
|
.irq_mask = MALIDP550_SE_IRQ_EOW |
|
|
MALIDP550_SE_IRQ_AXI_ERR,
|
|
},
|
|
.dc_irq_map = {
|
|
.irq_mask = MALIDP550_DC_IRQ_CONF_VALID,
|
|
.vsync_irq = MALIDP550_DC_IRQ_CONF_VALID,
|
|
},
|
|
.pixel_formats = malidp550_de_formats,
|
|
.n_pixel_formats = ARRAY_SIZE(malidp550_de_formats),
|
|
.bus_align_bytes = 8,
|
|
},
|
|
.query_hw = malidp550_query_hw,
|
|
.enter_config_mode = malidp550_enter_config_mode,
|
|
.leave_config_mode = malidp550_leave_config_mode,
|
|
.in_config_mode = malidp550_in_config_mode,
|
|
.set_config_valid = malidp550_set_config_valid,
|
|
.modeset = malidp550_modeset,
|
|
.rotmem_required = malidp550_rotmem_required,
|
|
.se_set_scaling_coeffs = malidp550_se_set_scaling_coeffs,
|
|
.se_calc_mclk = malidp550_se_calc_mclk,
|
|
.features = 0,
|
|
},
|
|
[MALIDP_650] = {
|
|
.map = {
|
|
.coeffs_base = MALIDP550_COEFFS_BASE,
|
|
.se_base = MALIDP550_SE_BASE,
|
|
.dc_base = MALIDP550_DC_BASE,
|
|
.out_depth_base = MALIDP550_DE_OUTPUT_DEPTH,
|
|
.features = MALIDP_REGMAP_HAS_CLEARIRQ,
|
|
.n_layers = ARRAY_SIZE(malidp550_layers),
|
|
.layers = malidp550_layers,
|
|
.de_irq_map = {
|
|
.irq_mask = MALIDP_DE_IRQ_UNDERRUN |
|
|
MALIDP650_DE_IRQ_DRIFT |
|
|
MALIDP550_DE_IRQ_VSYNC,
|
|
.vsync_irq = MALIDP550_DE_IRQ_VSYNC,
|
|
},
|
|
.se_irq_map = {
|
|
.irq_mask = MALIDP550_SE_IRQ_EOW |
|
|
MALIDP550_SE_IRQ_AXI_ERR,
|
|
},
|
|
.dc_irq_map = {
|
|
.irq_mask = MALIDP550_DC_IRQ_CONF_VALID,
|
|
.vsync_irq = MALIDP550_DC_IRQ_CONF_VALID,
|
|
},
|
|
.pixel_formats = malidp550_de_formats,
|
|
.n_pixel_formats = ARRAY_SIZE(malidp550_de_formats),
|
|
.bus_align_bytes = 16,
|
|
},
|
|
.query_hw = malidp650_query_hw,
|
|
.enter_config_mode = malidp550_enter_config_mode,
|
|
.leave_config_mode = malidp550_leave_config_mode,
|
|
.in_config_mode = malidp550_in_config_mode,
|
|
.set_config_valid = malidp550_set_config_valid,
|
|
.modeset = malidp550_modeset,
|
|
.rotmem_required = malidp550_rotmem_required,
|
|
.se_set_scaling_coeffs = malidp550_se_set_scaling_coeffs,
|
|
.se_calc_mclk = malidp550_se_calc_mclk,
|
|
.features = 0,
|
|
},
|
|
};
|
|
|
|
u8 malidp_hw_get_format_id(const struct malidp_hw_regmap *map,
|
|
u8 layer_id, u32 format)
|
|
{
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < map->n_pixel_formats; i++) {
|
|
if (((map->pixel_formats[i].layer & layer_id) == layer_id) &&
|
|
(map->pixel_formats[i].format == format))
|
|
return map->pixel_formats[i].id;
|
|
}
|
|
|
|
return MALIDP_INVALID_FORMAT_ID;
|
|
}
|
|
|
|
static void malidp_hw_clear_irq(struct malidp_hw_device *hwdev, u8 block, u32 irq)
|
|
{
|
|
u32 base = malidp_get_block_base(hwdev, block);
|
|
|
|
if (hwdev->hw->map.features & MALIDP_REGMAP_HAS_CLEARIRQ)
|
|
malidp_hw_write(hwdev, irq, base + MALIDP_REG_CLEARIRQ);
|
|
else
|
|
malidp_hw_write(hwdev, irq, base + MALIDP_REG_STATUS);
|
|
}
|
|
|
|
static irqreturn_t malidp_de_irq(int irq, void *arg)
|
|
{
|
|
struct drm_device *drm = arg;
|
|
struct malidp_drm *malidp = drm->dev_private;
|
|
struct malidp_hw_device *hwdev;
|
|
struct malidp_hw *hw;
|
|
const struct malidp_irq_map *de;
|
|
u32 status, mask, dc_status;
|
|
irqreturn_t ret = IRQ_NONE;
|
|
|
|
hwdev = malidp->dev;
|
|
hw = hwdev->hw;
|
|
de = &hw->map.de_irq_map;
|
|
|
|
/*
|
|
* if we are suspended it is likely that we were invoked because
|
|
* we share an interrupt line with some other driver, don't try
|
|
* to read the hardware registers
|
|
*/
|
|
if (hwdev->pm_suspended)
|
|
return IRQ_NONE;
|
|
|
|
/* first handle the config valid IRQ */
|
|
dc_status = malidp_hw_read(hwdev, hw->map.dc_base + MALIDP_REG_STATUS);
|
|
if (dc_status & hw->map.dc_irq_map.vsync_irq) {
|
|
malidp_hw_clear_irq(hwdev, MALIDP_DC_BLOCK, dc_status);
|
|
/* do we have a page flip event? */
|
|
if (malidp->event != NULL) {
|
|
spin_lock(&drm->event_lock);
|
|
drm_crtc_send_vblank_event(&malidp->crtc, malidp->event);
|
|
malidp->event = NULL;
|
|
spin_unlock(&drm->event_lock);
|
|
}
|
|
atomic_set(&malidp->config_valid, 1);
|
|
ret = IRQ_WAKE_THREAD;
|
|
}
|
|
|
|
status = malidp_hw_read(hwdev, MALIDP_REG_STATUS);
|
|
if (!(status & de->irq_mask))
|
|
return ret;
|
|
|
|
mask = malidp_hw_read(hwdev, MALIDP_REG_MASKIRQ);
|
|
status &= mask;
|
|
if ((status & de->vsync_irq) && malidp->crtc.enabled)
|
|
drm_crtc_handle_vblank(&malidp->crtc);
|
|
|
|
malidp_hw_clear_irq(hwdev, MALIDP_DE_BLOCK, status);
|
|
|
|
return (ret == IRQ_NONE) ? IRQ_HANDLED : ret;
|
|
}
|
|
|
|
static irqreturn_t malidp_de_irq_thread_handler(int irq, void *arg)
|
|
{
|
|
struct drm_device *drm = arg;
|
|
struct malidp_drm *malidp = drm->dev_private;
|
|
|
|
wake_up(&malidp->wq);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
int malidp_de_irq_init(struct drm_device *drm, int irq)
|
|
{
|
|
struct malidp_drm *malidp = drm->dev_private;
|
|
struct malidp_hw_device *hwdev = malidp->dev;
|
|
int ret;
|
|
|
|
/* ensure interrupts are disabled */
|
|
malidp_hw_disable_irq(hwdev, MALIDP_DE_BLOCK, 0xffffffff);
|
|
malidp_hw_clear_irq(hwdev, MALIDP_DE_BLOCK, 0xffffffff);
|
|
malidp_hw_disable_irq(hwdev, MALIDP_DC_BLOCK, 0xffffffff);
|
|
malidp_hw_clear_irq(hwdev, MALIDP_DC_BLOCK, 0xffffffff);
|
|
|
|
ret = devm_request_threaded_irq(drm->dev, irq, malidp_de_irq,
|
|
malidp_de_irq_thread_handler,
|
|
IRQF_SHARED, "malidp-de", drm);
|
|
if (ret < 0) {
|
|
DRM_ERROR("failed to install DE IRQ handler\n");
|
|
return ret;
|
|
}
|
|
|
|
/* first enable the DC block IRQs */
|
|
malidp_hw_enable_irq(hwdev, MALIDP_DC_BLOCK,
|
|
hwdev->hw->map.dc_irq_map.irq_mask);
|
|
|
|
/* now enable the DE block IRQs */
|
|
malidp_hw_enable_irq(hwdev, MALIDP_DE_BLOCK,
|
|
hwdev->hw->map.de_irq_map.irq_mask);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void malidp_de_irq_fini(struct drm_device *drm)
|
|
{
|
|
struct malidp_drm *malidp = drm->dev_private;
|
|
struct malidp_hw_device *hwdev = malidp->dev;
|
|
|
|
malidp_hw_disable_irq(hwdev, MALIDP_DE_BLOCK,
|
|
hwdev->hw->map.de_irq_map.irq_mask);
|
|
malidp_hw_disable_irq(hwdev, MALIDP_DC_BLOCK,
|
|
hwdev->hw->map.dc_irq_map.irq_mask);
|
|
}
|
|
|
|
static irqreturn_t malidp_se_irq(int irq, void *arg)
|
|
{
|
|
struct drm_device *drm = arg;
|
|
struct malidp_drm *malidp = drm->dev_private;
|
|
struct malidp_hw_device *hwdev = malidp->dev;
|
|
struct malidp_hw *hw = hwdev->hw;
|
|
const struct malidp_irq_map *se = &hw->map.se_irq_map;
|
|
u32 status, mask;
|
|
|
|
/*
|
|
* if we are suspended it is likely that we were invoked because
|
|
* we share an interrupt line with some other driver, don't try
|
|
* to read the hardware registers
|
|
*/
|
|
if (hwdev->pm_suspended)
|
|
return IRQ_NONE;
|
|
|
|
status = malidp_hw_read(hwdev, hw->map.se_base + MALIDP_REG_STATUS);
|
|
if (!(status & se->irq_mask))
|
|
return IRQ_NONE;
|
|
|
|
mask = malidp_hw_read(hwdev, hw->map.se_base + MALIDP_REG_MASKIRQ);
|
|
status = malidp_hw_read(hwdev, hw->map.se_base + MALIDP_REG_STATUS);
|
|
status &= mask;
|
|
/* ToDo: status decoding and firing up of VSYNC and page flip events */
|
|
|
|
malidp_hw_clear_irq(hwdev, MALIDP_SE_BLOCK, status);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static irqreturn_t malidp_se_irq_thread_handler(int irq, void *arg)
|
|
{
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
int malidp_se_irq_init(struct drm_device *drm, int irq)
|
|
{
|
|
struct malidp_drm *malidp = drm->dev_private;
|
|
struct malidp_hw_device *hwdev = malidp->dev;
|
|
int ret;
|
|
|
|
/* ensure interrupts are disabled */
|
|
malidp_hw_disable_irq(hwdev, MALIDP_SE_BLOCK, 0xffffffff);
|
|
malidp_hw_clear_irq(hwdev, MALIDP_SE_BLOCK, 0xffffffff);
|
|
|
|
ret = devm_request_threaded_irq(drm->dev, irq, malidp_se_irq,
|
|
malidp_se_irq_thread_handler,
|
|
IRQF_SHARED, "malidp-se", drm);
|
|
if (ret < 0) {
|
|
DRM_ERROR("failed to install SE IRQ handler\n");
|
|
return ret;
|
|
}
|
|
|
|
malidp_hw_enable_irq(hwdev, MALIDP_SE_BLOCK,
|
|
hwdev->hw->map.se_irq_map.irq_mask);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void malidp_se_irq_fini(struct drm_device *drm)
|
|
{
|
|
struct malidp_drm *malidp = drm->dev_private;
|
|
struct malidp_hw_device *hwdev = malidp->dev;
|
|
|
|
malidp_hw_disable_irq(hwdev, MALIDP_SE_BLOCK,
|
|
hwdev->hw->map.se_irq_map.irq_mask);
|
|
}
|