![Daniel Vetter](/assets/img/avatar_default.png)
It's dead code, the core handles all this directly now. The only special case is nouveau and tda988x which used one function for both legacy modeset code and -nv50 atomic world instead of 2 vtables. But amounts to exactly the same. v2: Rebase over the panel/brideg refactorings in stm/ltdc. Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Cc: Archit Taneja <architt@codeaurora.org> Cc: Andrzej Hajda <a.hajda@samsung.com> Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com> Cc: Peter Senna Tschudin <peter.senna@collabora.com> Cc: Martin Donnelly <martin.donnelly@ge.com> Cc: Martyn Welch <martyn.welch@collabora.co.uk> Cc: Daniel Vetter <daniel.vetter@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Sean Paul <seanpaul@chromium.org> Cc: David Airlie <airlied@linux.ie> Cc: Inki Dae <inki.dae@samsung.com> Cc: Joonyoung Shim <jy0922.shim@samsung.com> Cc: Seung-Woo Kim <sw0312.kim@samsung.com> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Kukjin Kim <kgene@kernel.org> Cc: Krzysztof Kozlowski <krzk@kernel.org> Cc: Stefan Agner <stefan@agner.ch> Cc: Alison Wang <alison.wang@freescale.com> Cc: Russell King <linux@armlinux.org.uk> Cc: Philipp Zabel <p.zabel@pengutronix.de> Cc: CK Hu <ck.hu@mediatek.com> Cc: Matthias Brugger <matthias.bgg@gmail.com> Cc: Neil Armstrong <narmstrong@baylibre.com> Cc: Carlo Caione <carlo@caione.org> Cc: Kevin Hilman <khilman@baylibre.com> Cc: Marek Vasut <marex@denx.de> Cc: Ben Skeggs <bskeggs@redhat.com> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: Eric Anholt <eric@anholt.net> Cc: Mark Yao <mark.yao@rock-chips.com> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Benjamin Gaignard <benjamin.gaignard@linaro.org> Cc: Vincent Abriou <vincent.abriou@st.com> Cc: Yannick Fertre <yannick.fertre@st.com> Cc: Philippe Cornu <philippe.cornu@st.com> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Chen-Yu Tsai <wens@csie.org> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: Jyri Sarha <jsarha@ti.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: John Stultz <john.stultz@linaro.org> Cc: Lars-Peter Clausen <lars@metafoo.de> Cc: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Cc: Jeffy Chen <jeffy.chen@rock-chips.com> Cc: Tomeu Vizoso <tomeu.vizoso@collabora.com> Cc: Yakir Yang <kuankuan.y@gmail.com> Cc: Marek Szyprowski <m.szyprowski@samsung.com> Cc: Jose Abreu <Jose.Abreu@synopsys.com> Cc: Romain Perier <romain.perier@collabora.com> Cc: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Cc: Xinliang Liu <z.liuxinliang@hisilicon.com> Cc: Alexey Brodkin <abrodkin@synopsys.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Rongrong Zou <zourongrong@gmail.com> Cc: Rob Clark <robdclark@gmail.com> Cc: Hai Li <hali@codeaurora.org> Cc: "Noralf Trønnes" <noralf@tronnes.org> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Cc: intel-gfx@lists.freedesktop.org Cc: linux-mediatek@lists.infradead.org Cc: linux-amlogic@lists.infradead.org Cc: nouveau@lists.freedesktop.org Cc: linux-renesas-soc@vger.kernel.org Cc: linux-rockchip@lists.infradead.org Cc: linux-tegra@vger.kernel.org Cc: virtualization@lists.linux-foundation.org Cc: zain wang <wzz@rock-chips.com> Cc: Baoyou Xie <baoyou.xie@linaro.org> Cc: Boris Brezillon <boris.brezillon@free-electrons.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170725080122.20548-8-daniel.vetter@ffwll.ch Acked-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Archit Taneja <architt@codeaurora.org> Tested-by: Philippe Cornu <philippe.cornu@st.com> (on stm) Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Acked-by: Shawn Guo <shawnguo@kernel.org> Acked-by: Noralf Trønnes <noralf@tronnes.org> Acked-by: Vincent Abriou <vincent.abriou@st.com>
717 lines
17 KiB
C
717 lines
17 KiB
C
/*
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* i.MX drm driver - Television Encoder (TVEv2)
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*
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* Copyright (C) 2013 Philipp Zabel, Pengutronix
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/component.h>
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#include <linux/module.h>
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#include <linux/i2c.h>
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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#include <linux/spinlock.h>
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#include <linux/videodev2.h>
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#include <drm/drmP.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_fb_helper.h>
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#include <drm/drm_crtc_helper.h>
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#include <video/imx-ipu-v3.h>
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#include "imx-drm.h"
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#define TVE_COM_CONF_REG 0x00
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#define TVE_TVDAC0_CONT_REG 0x28
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#define TVE_TVDAC1_CONT_REG 0x2c
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#define TVE_TVDAC2_CONT_REG 0x30
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#define TVE_CD_CONT_REG 0x34
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#define TVE_INT_CONT_REG 0x64
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#define TVE_STAT_REG 0x68
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#define TVE_TST_MODE_REG 0x6c
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#define TVE_MV_CONT_REG 0xdc
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/* TVE_COM_CONF_REG */
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#define TVE_SYNC_CH_2_EN BIT(22)
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#define TVE_SYNC_CH_1_EN BIT(21)
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#define TVE_SYNC_CH_0_EN BIT(20)
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#define TVE_TV_OUT_MODE_MASK (0x7 << 12)
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#define TVE_TV_OUT_DISABLE (0x0 << 12)
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#define TVE_TV_OUT_CVBS_0 (0x1 << 12)
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#define TVE_TV_OUT_CVBS_2 (0x2 << 12)
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#define TVE_TV_OUT_CVBS_0_2 (0x3 << 12)
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#define TVE_TV_OUT_SVIDEO_0_1 (0x4 << 12)
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#define TVE_TV_OUT_SVIDEO_0_1_CVBS2_2 (0x5 << 12)
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#define TVE_TV_OUT_YPBPR (0x6 << 12)
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#define TVE_TV_OUT_RGB (0x7 << 12)
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#define TVE_TV_STAND_MASK (0xf << 8)
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#define TVE_TV_STAND_HD_1080P30 (0xc << 8)
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#define TVE_P2I_CONV_EN BIT(7)
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#define TVE_INP_VIDEO_FORM BIT(6)
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#define TVE_INP_YCBCR_422 (0x0 << 6)
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#define TVE_INP_YCBCR_444 (0x1 << 6)
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#define TVE_DATA_SOURCE_MASK (0x3 << 4)
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#define TVE_DATA_SOURCE_BUS1 (0x0 << 4)
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#define TVE_DATA_SOURCE_BUS2 (0x1 << 4)
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#define TVE_DATA_SOURCE_EXT (0x2 << 4)
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#define TVE_DATA_SOURCE_TESTGEN (0x3 << 4)
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#define TVE_IPU_CLK_EN_OFS 3
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#define TVE_IPU_CLK_EN BIT(3)
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#define TVE_DAC_SAMP_RATE_OFS 1
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#define TVE_DAC_SAMP_RATE_WIDTH 2
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#define TVE_DAC_SAMP_RATE_MASK (0x3 << 1)
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#define TVE_DAC_FULL_RATE (0x0 << 1)
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#define TVE_DAC_DIV2_RATE (0x1 << 1)
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#define TVE_DAC_DIV4_RATE (0x2 << 1)
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#define TVE_EN BIT(0)
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/* TVE_TVDACx_CONT_REG */
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#define TVE_TVDAC_GAIN_MASK (0x3f << 0)
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/* TVE_CD_CONT_REG */
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#define TVE_CD_CH_2_SM_EN BIT(22)
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#define TVE_CD_CH_1_SM_EN BIT(21)
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#define TVE_CD_CH_0_SM_EN BIT(20)
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#define TVE_CD_CH_2_LM_EN BIT(18)
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#define TVE_CD_CH_1_LM_EN BIT(17)
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#define TVE_CD_CH_0_LM_EN BIT(16)
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#define TVE_CD_CH_2_REF_LVL BIT(10)
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#define TVE_CD_CH_1_REF_LVL BIT(9)
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#define TVE_CD_CH_0_REF_LVL BIT(8)
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#define TVE_CD_EN BIT(0)
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/* TVE_INT_CONT_REG */
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#define TVE_FRAME_END_IEN BIT(13)
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#define TVE_CD_MON_END_IEN BIT(2)
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#define TVE_CD_SM_IEN BIT(1)
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#define TVE_CD_LM_IEN BIT(0)
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/* TVE_TST_MODE_REG */
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#define TVE_TVDAC_TEST_MODE_MASK (0x7 << 0)
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#define IMX_TVE_DAC_VOLTAGE 2750000
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enum {
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TVE_MODE_TVOUT,
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TVE_MODE_VGA,
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};
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struct imx_tve {
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struct drm_connector connector;
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struct drm_encoder encoder;
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struct device *dev;
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spinlock_t lock; /* register lock */
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bool enabled;
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int mode;
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int di_hsync_pin;
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int di_vsync_pin;
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struct regmap *regmap;
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struct regulator *dac_reg;
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struct i2c_adapter *ddc;
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struct clk *clk;
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struct clk *di_sel_clk;
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struct clk_hw clk_hw_di;
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struct clk *di_clk;
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};
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static inline struct imx_tve *con_to_tve(struct drm_connector *c)
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{
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return container_of(c, struct imx_tve, connector);
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}
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static inline struct imx_tve *enc_to_tve(struct drm_encoder *e)
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{
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return container_of(e, struct imx_tve, encoder);
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}
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static void tve_lock(void *__tve)
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__acquires(&tve->lock)
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{
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struct imx_tve *tve = __tve;
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spin_lock(&tve->lock);
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}
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static void tve_unlock(void *__tve)
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__releases(&tve->lock)
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{
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struct imx_tve *tve = __tve;
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spin_unlock(&tve->lock);
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}
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static void tve_enable(struct imx_tve *tve)
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{
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if (!tve->enabled) {
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tve->enabled = true;
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clk_prepare_enable(tve->clk);
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regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
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TVE_EN, TVE_EN);
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}
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/* clear interrupt status register */
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regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
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/* cable detection irq disabled in VGA mode, enabled in TVOUT mode */
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if (tve->mode == TVE_MODE_VGA)
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regmap_write(tve->regmap, TVE_INT_CONT_REG, 0);
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else
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regmap_write(tve->regmap, TVE_INT_CONT_REG,
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TVE_CD_SM_IEN |
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TVE_CD_LM_IEN |
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TVE_CD_MON_END_IEN);
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}
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static void tve_disable(struct imx_tve *tve)
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{
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if (tve->enabled) {
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tve->enabled = false;
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regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, TVE_EN, 0);
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clk_disable_unprepare(tve->clk);
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}
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}
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static int tve_setup_tvout(struct imx_tve *tve)
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{
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return -ENOTSUPP;
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}
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static int tve_setup_vga(struct imx_tve *tve)
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{
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unsigned int mask;
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unsigned int val;
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int ret;
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/* set gain to (1 + 10/128) to provide 0.7V peak-to-peak amplitude */
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ret = regmap_update_bits(tve->regmap, TVE_TVDAC0_CONT_REG,
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TVE_TVDAC_GAIN_MASK, 0x0a);
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if (ret)
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return ret;
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ret = regmap_update_bits(tve->regmap, TVE_TVDAC1_CONT_REG,
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TVE_TVDAC_GAIN_MASK, 0x0a);
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if (ret)
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return ret;
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ret = regmap_update_bits(tve->regmap, TVE_TVDAC2_CONT_REG,
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TVE_TVDAC_GAIN_MASK, 0x0a);
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if (ret)
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return ret;
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/* set configuration register */
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mask = TVE_DATA_SOURCE_MASK | TVE_INP_VIDEO_FORM;
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val = TVE_DATA_SOURCE_BUS2 | TVE_INP_YCBCR_444;
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mask |= TVE_TV_STAND_MASK | TVE_P2I_CONV_EN;
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val |= TVE_TV_STAND_HD_1080P30 | 0;
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mask |= TVE_TV_OUT_MODE_MASK | TVE_SYNC_CH_0_EN;
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val |= TVE_TV_OUT_RGB | TVE_SYNC_CH_0_EN;
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ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, mask, val);
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if (ret)
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return ret;
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/* set test mode (as documented) */
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return regmap_update_bits(tve->regmap, TVE_TST_MODE_REG,
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TVE_TVDAC_TEST_MODE_MASK, 1);
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}
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static int imx_tve_connector_get_modes(struct drm_connector *connector)
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{
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struct imx_tve *tve = con_to_tve(connector);
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struct edid *edid;
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int ret = 0;
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if (!tve->ddc)
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return 0;
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edid = drm_get_edid(connector, tve->ddc);
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if (edid) {
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drm_mode_connector_update_edid_property(connector, edid);
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ret = drm_add_edid_modes(connector, edid);
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kfree(edid);
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}
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return ret;
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}
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static int imx_tve_connector_mode_valid(struct drm_connector *connector,
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struct drm_display_mode *mode)
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{
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struct imx_tve *tve = con_to_tve(connector);
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unsigned long rate;
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/* pixel clock with 2x oversampling */
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rate = clk_round_rate(tve->clk, 2000UL * mode->clock) / 2000;
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if (rate == mode->clock)
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return MODE_OK;
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/* pixel clock without oversampling */
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rate = clk_round_rate(tve->clk, 1000UL * mode->clock) / 1000;
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if (rate == mode->clock)
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return MODE_OK;
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dev_warn(tve->dev, "ignoring mode %dx%d\n",
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mode->hdisplay, mode->vdisplay);
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return MODE_BAD;
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}
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static struct drm_encoder *imx_tve_connector_best_encoder(
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struct drm_connector *connector)
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{
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struct imx_tve *tve = con_to_tve(connector);
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return &tve->encoder;
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}
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static void imx_tve_encoder_mode_set(struct drm_encoder *encoder,
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struct drm_display_mode *orig_mode,
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struct drm_display_mode *mode)
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{
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struct imx_tve *tve = enc_to_tve(encoder);
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unsigned long rounded_rate;
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unsigned long rate;
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int div = 1;
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int ret;
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/*
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* FIXME
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* we should try 4k * mode->clock first,
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* and enable 4x oversampling for lower resolutions
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*/
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rate = 2000UL * mode->clock;
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clk_set_rate(tve->clk, rate);
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rounded_rate = clk_get_rate(tve->clk);
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if (rounded_rate >= rate)
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div = 2;
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clk_set_rate(tve->di_clk, rounded_rate / div);
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ret = clk_set_parent(tve->di_sel_clk, tve->di_clk);
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if (ret < 0) {
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dev_err(tve->dev, "failed to set di_sel parent to tve_di: %d\n",
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ret);
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}
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regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
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TVE_IPU_CLK_EN, TVE_IPU_CLK_EN);
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if (tve->mode == TVE_MODE_VGA)
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ret = tve_setup_vga(tve);
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else
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ret = tve_setup_tvout(tve);
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if (ret)
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dev_err(tve->dev, "failed to set configuration: %d\n", ret);
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}
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static void imx_tve_encoder_enable(struct drm_encoder *encoder)
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{
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struct imx_tve *tve = enc_to_tve(encoder);
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tve_enable(tve);
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}
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static void imx_tve_encoder_disable(struct drm_encoder *encoder)
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{
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struct imx_tve *tve = enc_to_tve(encoder);
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tve_disable(tve);
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}
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static int imx_tve_atomic_check(struct drm_encoder *encoder,
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struct drm_crtc_state *crtc_state,
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struct drm_connector_state *conn_state)
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{
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struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
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struct imx_tve *tve = enc_to_tve(encoder);
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imx_crtc_state->bus_format = MEDIA_BUS_FMT_GBR888_1X24;
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imx_crtc_state->di_hsync_pin = tve->di_hsync_pin;
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imx_crtc_state->di_vsync_pin = tve->di_vsync_pin;
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return 0;
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}
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static const struct drm_connector_funcs imx_tve_connector_funcs = {
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.fill_modes = drm_helper_probe_single_connector_modes,
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.destroy = imx_drm_connector_destroy,
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.reset = drm_atomic_helper_connector_reset,
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.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
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.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
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};
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static const struct drm_connector_helper_funcs imx_tve_connector_helper_funcs = {
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.get_modes = imx_tve_connector_get_modes,
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.best_encoder = imx_tve_connector_best_encoder,
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.mode_valid = imx_tve_connector_mode_valid,
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};
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static const struct drm_encoder_funcs imx_tve_encoder_funcs = {
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.destroy = imx_drm_encoder_destroy,
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};
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static const struct drm_encoder_helper_funcs imx_tve_encoder_helper_funcs = {
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.mode_set = imx_tve_encoder_mode_set,
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.enable = imx_tve_encoder_enable,
|
|
.disable = imx_tve_encoder_disable,
|
|
.atomic_check = imx_tve_atomic_check,
|
|
};
|
|
|
|
static irqreturn_t imx_tve_irq_handler(int irq, void *data)
|
|
{
|
|
struct imx_tve *tve = data;
|
|
unsigned int val;
|
|
|
|
regmap_read(tve->regmap, TVE_STAT_REG, &val);
|
|
|
|
/* clear interrupt status register */
|
|
regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static unsigned long clk_tve_di_recalc_rate(struct clk_hw *hw,
|
|
unsigned long parent_rate)
|
|
{
|
|
struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
|
|
unsigned int val;
|
|
int ret;
|
|
|
|
ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
|
|
if (ret < 0)
|
|
return 0;
|
|
|
|
switch (val & TVE_DAC_SAMP_RATE_MASK) {
|
|
case TVE_DAC_DIV4_RATE:
|
|
return parent_rate / 4;
|
|
case TVE_DAC_DIV2_RATE:
|
|
return parent_rate / 2;
|
|
case TVE_DAC_FULL_RATE:
|
|
default:
|
|
return parent_rate;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static long clk_tve_di_round_rate(struct clk_hw *hw, unsigned long rate,
|
|
unsigned long *prate)
|
|
{
|
|
unsigned long div;
|
|
|
|
div = *prate / rate;
|
|
if (div >= 4)
|
|
return *prate / 4;
|
|
else if (div >= 2)
|
|
return *prate / 2;
|
|
return *prate;
|
|
}
|
|
|
|
static int clk_tve_di_set_rate(struct clk_hw *hw, unsigned long rate,
|
|
unsigned long parent_rate)
|
|
{
|
|
struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
|
|
unsigned long div;
|
|
u32 val;
|
|
int ret;
|
|
|
|
div = parent_rate / rate;
|
|
if (div >= 4)
|
|
val = TVE_DAC_DIV4_RATE;
|
|
else if (div >= 2)
|
|
val = TVE_DAC_DIV2_RATE;
|
|
else
|
|
val = TVE_DAC_FULL_RATE;
|
|
|
|
ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
|
|
TVE_DAC_SAMP_RATE_MASK, val);
|
|
|
|
if (ret < 0) {
|
|
dev_err(tve->dev, "failed to set divider: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct clk_ops clk_tve_di_ops = {
|
|
.round_rate = clk_tve_di_round_rate,
|
|
.set_rate = clk_tve_di_set_rate,
|
|
.recalc_rate = clk_tve_di_recalc_rate,
|
|
};
|
|
|
|
static int tve_clk_init(struct imx_tve *tve, void __iomem *base)
|
|
{
|
|
const char *tve_di_parent[1];
|
|
struct clk_init_data init = {
|
|
.name = "tve_di",
|
|
.ops = &clk_tve_di_ops,
|
|
.num_parents = 1,
|
|
.flags = 0,
|
|
};
|
|
|
|
tve_di_parent[0] = __clk_get_name(tve->clk);
|
|
init.parent_names = (const char **)&tve_di_parent;
|
|
|
|
tve->clk_hw_di.init = &init;
|
|
tve->di_clk = clk_register(tve->dev, &tve->clk_hw_di);
|
|
if (IS_ERR(tve->di_clk)) {
|
|
dev_err(tve->dev, "failed to register TVE output clock: %ld\n",
|
|
PTR_ERR(tve->di_clk));
|
|
return PTR_ERR(tve->di_clk);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int imx_tve_register(struct drm_device *drm, struct imx_tve *tve)
|
|
{
|
|
int encoder_type;
|
|
int ret;
|
|
|
|
encoder_type = tve->mode == TVE_MODE_VGA ?
|
|
DRM_MODE_ENCODER_DAC : DRM_MODE_ENCODER_TVDAC;
|
|
|
|
ret = imx_drm_encoder_parse_of(drm, &tve->encoder, tve->dev->of_node);
|
|
if (ret)
|
|
return ret;
|
|
|
|
drm_encoder_helper_add(&tve->encoder, &imx_tve_encoder_helper_funcs);
|
|
drm_encoder_init(drm, &tve->encoder, &imx_tve_encoder_funcs,
|
|
encoder_type, NULL);
|
|
|
|
drm_connector_helper_add(&tve->connector,
|
|
&imx_tve_connector_helper_funcs);
|
|
drm_connector_init(drm, &tve->connector, &imx_tve_connector_funcs,
|
|
DRM_MODE_CONNECTOR_VGA);
|
|
|
|
drm_mode_connector_attach_encoder(&tve->connector, &tve->encoder);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static bool imx_tve_readable_reg(struct device *dev, unsigned int reg)
|
|
{
|
|
return (reg % 4 == 0) && (reg <= 0xdc);
|
|
}
|
|
|
|
static struct regmap_config tve_regmap_config = {
|
|
.reg_bits = 32,
|
|
.val_bits = 32,
|
|
.reg_stride = 4,
|
|
|
|
.readable_reg = imx_tve_readable_reg,
|
|
|
|
.lock = tve_lock,
|
|
.unlock = tve_unlock,
|
|
|
|
.max_register = 0xdc,
|
|
};
|
|
|
|
static const char * const imx_tve_modes[] = {
|
|
[TVE_MODE_TVOUT] = "tvout",
|
|
[TVE_MODE_VGA] = "vga",
|
|
};
|
|
|
|
static const int of_get_tve_mode(struct device_node *np)
|
|
{
|
|
const char *bm;
|
|
int ret, i;
|
|
|
|
ret = of_property_read_string(np, "fsl,tve-mode", &bm);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(imx_tve_modes); i++)
|
|
if (!strcasecmp(bm, imx_tve_modes[i]))
|
|
return i;
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
static int imx_tve_bind(struct device *dev, struct device *master, void *data)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
struct drm_device *drm = data;
|
|
struct device_node *np = dev->of_node;
|
|
struct device_node *ddc_node;
|
|
struct imx_tve *tve;
|
|
struct resource *res;
|
|
void __iomem *base;
|
|
unsigned int val;
|
|
int irq;
|
|
int ret;
|
|
|
|
tve = devm_kzalloc(dev, sizeof(*tve), GFP_KERNEL);
|
|
if (!tve)
|
|
return -ENOMEM;
|
|
|
|
tve->dev = dev;
|
|
spin_lock_init(&tve->lock);
|
|
|
|
ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
|
|
if (ddc_node) {
|
|
tve->ddc = of_find_i2c_adapter_by_node(ddc_node);
|
|
of_node_put(ddc_node);
|
|
}
|
|
|
|
tve->mode = of_get_tve_mode(np);
|
|
if (tve->mode != TVE_MODE_VGA) {
|
|
dev_err(dev, "only VGA mode supported, currently\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (tve->mode == TVE_MODE_VGA) {
|
|
ret = of_property_read_u32(np, "fsl,hsync-pin",
|
|
&tve->di_hsync_pin);
|
|
|
|
if (ret < 0) {
|
|
dev_err(dev, "failed to get hsync pin\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = of_property_read_u32(np, "fsl,vsync-pin",
|
|
&tve->di_vsync_pin);
|
|
|
|
if (ret < 0) {
|
|
dev_err(dev, "failed to get vsync pin\n");
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
base = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(base))
|
|
return PTR_ERR(base);
|
|
|
|
tve_regmap_config.lock_arg = tve;
|
|
tve->regmap = devm_regmap_init_mmio_clk(dev, "tve", base,
|
|
&tve_regmap_config);
|
|
if (IS_ERR(tve->regmap)) {
|
|
dev_err(dev, "failed to init regmap: %ld\n",
|
|
PTR_ERR(tve->regmap));
|
|
return PTR_ERR(tve->regmap);
|
|
}
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0) {
|
|
dev_err(dev, "failed to get irq\n");
|
|
return irq;
|
|
}
|
|
|
|
ret = devm_request_threaded_irq(dev, irq, NULL,
|
|
imx_tve_irq_handler, IRQF_ONESHOT,
|
|
"imx-tve", tve);
|
|
if (ret < 0) {
|
|
dev_err(dev, "failed to request irq: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
tve->dac_reg = devm_regulator_get(dev, "dac");
|
|
if (!IS_ERR(tve->dac_reg)) {
|
|
if (regulator_get_voltage(tve->dac_reg) != IMX_TVE_DAC_VOLTAGE)
|
|
dev_warn(dev, "dac voltage is not %d uV\n", IMX_TVE_DAC_VOLTAGE);
|
|
ret = regulator_enable(tve->dac_reg);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
tve->clk = devm_clk_get(dev, "tve");
|
|
if (IS_ERR(tve->clk)) {
|
|
dev_err(dev, "failed to get high speed tve clock: %ld\n",
|
|
PTR_ERR(tve->clk));
|
|
return PTR_ERR(tve->clk);
|
|
}
|
|
|
|
/* this is the IPU DI clock input selector, can be parented to tve_di */
|
|
tve->di_sel_clk = devm_clk_get(dev, "di_sel");
|
|
if (IS_ERR(tve->di_sel_clk)) {
|
|
dev_err(dev, "failed to get ipu di mux clock: %ld\n",
|
|
PTR_ERR(tve->di_sel_clk));
|
|
return PTR_ERR(tve->di_sel_clk);
|
|
}
|
|
|
|
ret = tve_clk_init(tve, base);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
|
|
if (ret < 0) {
|
|
dev_err(dev, "failed to read configuration register: %d\n",
|
|
ret);
|
|
return ret;
|
|
}
|
|
if (val != 0x00100000) {
|
|
dev_err(dev, "configuration register default value indicates this is not a TVEv2\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
/* disable cable detection for VGA mode */
|
|
ret = regmap_write(tve->regmap, TVE_CD_CONT_REG, 0);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = imx_tve_register(drm, tve);
|
|
if (ret)
|
|
return ret;
|
|
|
|
dev_set_drvdata(dev, tve);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void imx_tve_unbind(struct device *dev, struct device *master,
|
|
void *data)
|
|
{
|
|
struct imx_tve *tve = dev_get_drvdata(dev);
|
|
|
|
if (!IS_ERR(tve->dac_reg))
|
|
regulator_disable(tve->dac_reg);
|
|
}
|
|
|
|
static const struct component_ops imx_tve_ops = {
|
|
.bind = imx_tve_bind,
|
|
.unbind = imx_tve_unbind,
|
|
};
|
|
|
|
static int imx_tve_probe(struct platform_device *pdev)
|
|
{
|
|
return component_add(&pdev->dev, &imx_tve_ops);
|
|
}
|
|
|
|
static int imx_tve_remove(struct platform_device *pdev)
|
|
{
|
|
component_del(&pdev->dev, &imx_tve_ops);
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id imx_tve_dt_ids[] = {
|
|
{ .compatible = "fsl,imx53-tve", },
|
|
{ /* sentinel */ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, imx_tve_dt_ids);
|
|
|
|
static struct platform_driver imx_tve_driver = {
|
|
.probe = imx_tve_probe,
|
|
.remove = imx_tve_remove,
|
|
.driver = {
|
|
.of_match_table = imx_tve_dt_ids,
|
|
.name = "imx-tve",
|
|
},
|
|
};
|
|
|
|
module_platform_driver(imx_tve_driver);
|
|
|
|
MODULE_DESCRIPTION("i.MX Television Encoder driver");
|
|
MODULE_AUTHOR("Philipp Zabel, Pengutronix");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS("platform:imx-tve");
|