![Tomi Valkeinen](/assets/img/avatar_default.png)
We define max width and height in mode_config to 2048. These maximums affect many things, which are independent and depend on platform. We need to do more fine grained checks in the code paths for each component, and so the maximum values in mode_config should just be "big enough" to cover all use cases. Change the maximum width & height to 8192. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
780 lines
19 KiB
C
780 lines
19 KiB
C
/*
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* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
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* Author: Rob Clark <rob@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/sys_soc.h>
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#include <drm/drm_atomic.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_fb_helper.h>
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#include "omap_dmm_tiler.h"
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#include "omap_drv.h"
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#define DRIVER_NAME MODULE_NAME
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#define DRIVER_DESC "OMAP DRM"
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#define DRIVER_DATE "20110917"
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#define DRIVER_MAJOR 1
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#define DRIVER_MINOR 0
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#define DRIVER_PATCHLEVEL 0
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/*
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* mode config funcs
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*/
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/* Notes about mapping DSS and DRM entities:
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* CRTC: overlay
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* encoder: manager.. with some extension to allow one primary CRTC
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* and zero or more video CRTC's to be mapped to one encoder?
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* connector: dssdev.. manager can be attached/detached from different
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* devices
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*/
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static void omap_atomic_wait_for_completion(struct drm_device *dev,
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struct drm_atomic_state *old_state)
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{
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struct drm_crtc_state *new_crtc_state;
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struct drm_crtc *crtc;
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unsigned int i;
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int ret;
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for_each_new_crtc_in_state(old_state, crtc, new_crtc_state, i) {
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if (!new_crtc_state->active)
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continue;
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ret = omap_crtc_wait_pending(crtc);
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if (!ret)
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dev_warn(dev->dev,
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"atomic complete timeout (pipe %u)!\n", i);
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}
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}
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static void omap_atomic_commit_tail(struct drm_atomic_state *old_state)
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{
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struct drm_device *dev = old_state->dev;
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struct omap_drm_private *priv = dev->dev_private;
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priv->dispc_ops->runtime_get(priv->dispc);
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/* Apply the atomic update. */
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drm_atomic_helper_commit_modeset_disables(dev, old_state);
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if (priv->omaprev != 0x3430) {
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/* With the current dss dispc implementation we have to enable
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* the new modeset before we can commit planes. The dispc ovl
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* configuration relies on the video mode configuration been
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* written into the HW when the ovl configuration is
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* calculated.
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*
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* This approach is not ideal because after a mode change the
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* plane update is executed only after the first vblank
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* interrupt. The dispc implementation should be fixed so that
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* it is able use uncommitted drm state information.
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*/
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drm_atomic_helper_commit_modeset_enables(dev, old_state);
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omap_atomic_wait_for_completion(dev, old_state);
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drm_atomic_helper_commit_planes(dev, old_state, 0);
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drm_atomic_helper_commit_hw_done(old_state);
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} else {
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/*
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* OMAP3 DSS seems to have issues with the work-around above,
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* resulting in endless sync losts if a crtc is enabled without
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* a plane. For now, skip the WA for OMAP3.
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*/
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drm_atomic_helper_commit_planes(dev, old_state, 0);
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drm_atomic_helper_commit_modeset_enables(dev, old_state);
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drm_atomic_helper_commit_hw_done(old_state);
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}
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/*
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* Wait for completion of the page flips to ensure that old buffers
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* can't be touched by the hardware anymore before cleaning up planes.
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*/
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omap_atomic_wait_for_completion(dev, old_state);
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drm_atomic_helper_cleanup_planes(dev, old_state);
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priv->dispc_ops->runtime_put(priv->dispc);
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}
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static const struct drm_mode_config_helper_funcs omap_mode_config_helper_funcs = {
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.atomic_commit_tail = omap_atomic_commit_tail,
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};
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static const struct drm_mode_config_funcs omap_mode_config_funcs = {
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.fb_create = omap_framebuffer_create,
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.output_poll_changed = drm_fb_helper_output_poll_changed,
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.atomic_check = drm_atomic_helper_check,
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.atomic_commit = drm_atomic_helper_commit,
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};
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static int get_connector_type(struct omap_dss_device *dssdev)
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{
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switch (dssdev->type) {
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case OMAP_DISPLAY_TYPE_HDMI:
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return DRM_MODE_CONNECTOR_HDMIA;
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case OMAP_DISPLAY_TYPE_DVI:
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return DRM_MODE_CONNECTOR_DVID;
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case OMAP_DISPLAY_TYPE_DSI:
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return DRM_MODE_CONNECTOR_DSI;
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case OMAP_DISPLAY_TYPE_DPI:
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case OMAP_DISPLAY_TYPE_DBI:
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return DRM_MODE_CONNECTOR_DPI;
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case OMAP_DISPLAY_TYPE_VENC:
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/* TODO: This could also be composite */
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return DRM_MODE_CONNECTOR_SVIDEO;
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case OMAP_DISPLAY_TYPE_SDI:
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return DRM_MODE_CONNECTOR_LVDS;
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default:
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return DRM_MODE_CONNECTOR_Unknown;
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}
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}
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static void omap_disconnect_dssdevs(void)
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{
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struct omap_dss_device *dssdev = NULL;
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for_each_dss_dev(dssdev)
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dssdev->driver->disconnect(dssdev);
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}
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static int omap_connect_dssdevs(void)
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{
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int r;
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struct omap_dss_device *dssdev = NULL;
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if (!omapdss_stack_is_ready())
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return -EPROBE_DEFER;
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for_each_dss_dev(dssdev) {
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r = dssdev->driver->connect(dssdev);
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if (r == -EPROBE_DEFER) {
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omap_dss_put_device(dssdev);
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goto cleanup;
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} else if (r) {
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dev_warn(dssdev->dev, "could not connect display: %s\n",
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dssdev->name);
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}
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}
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return 0;
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cleanup:
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/*
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* if we are deferring probe, we disconnect the devices we previously
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* connected
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*/
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omap_disconnect_dssdevs();
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return r;
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}
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static int omap_modeset_init_properties(struct drm_device *dev)
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{
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struct omap_drm_private *priv = dev->dev_private;
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unsigned int num_planes = priv->dispc_ops->get_num_ovls(priv->dispc);
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priv->zorder_prop = drm_property_create_range(dev, 0, "zorder", 0,
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num_planes - 1);
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if (!priv->zorder_prop)
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return -ENOMEM;
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return 0;
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}
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static int omap_modeset_init(struct drm_device *dev)
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{
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struct omap_drm_private *priv = dev->dev_private;
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struct omap_dss_device *dssdev = NULL;
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int num_ovls = priv->dispc_ops->get_num_ovls(priv->dispc);
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int num_mgrs = priv->dispc_ops->get_num_mgrs(priv->dispc);
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int num_crtcs, crtc_idx, plane_idx;
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int ret;
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u32 plane_crtc_mask;
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drm_mode_config_init(dev);
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ret = omap_modeset_init_properties(dev);
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if (ret < 0)
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return ret;
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/*
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* This function creates exactly one connector, encoder, crtc,
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* and primary plane per each connected dss-device. Each
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* connector->encoder->crtc chain is expected to be separate
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* and each crtc is connect to a single dss-channel. If the
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* configuration does not match the expectations or exceeds
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* the available resources, the configuration is rejected.
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*/
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num_crtcs = 0;
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for_each_dss_dev(dssdev)
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if (omapdss_device_is_connected(dssdev))
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num_crtcs++;
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if (num_crtcs > num_mgrs || num_crtcs > num_ovls ||
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num_crtcs > ARRAY_SIZE(priv->crtcs) ||
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num_crtcs > ARRAY_SIZE(priv->planes) ||
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num_crtcs > ARRAY_SIZE(priv->encoders) ||
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num_crtcs > ARRAY_SIZE(priv->connectors)) {
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dev_err(dev->dev, "%s(): Too many connected displays\n",
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__func__);
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return -EINVAL;
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}
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/* All planes can be put to any CRTC */
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plane_crtc_mask = (1 << num_crtcs) - 1;
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dssdev = NULL;
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crtc_idx = 0;
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plane_idx = 0;
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for_each_dss_dev(dssdev) {
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struct drm_connector *connector;
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struct drm_encoder *encoder;
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struct drm_plane *plane;
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struct drm_crtc *crtc;
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if (!omapdss_device_is_connected(dssdev))
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continue;
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encoder = omap_encoder_init(dev, dssdev);
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if (!encoder)
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return -ENOMEM;
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connector = omap_connector_init(dev,
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get_connector_type(dssdev), dssdev, encoder);
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if (!connector)
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return -ENOMEM;
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plane = omap_plane_init(dev, plane_idx, DRM_PLANE_TYPE_PRIMARY,
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plane_crtc_mask);
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if (IS_ERR(plane))
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return PTR_ERR(plane);
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crtc = omap_crtc_init(dev, plane, dssdev);
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if (IS_ERR(crtc))
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return PTR_ERR(crtc);
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drm_mode_connector_attach_encoder(connector, encoder);
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encoder->possible_crtcs = (1 << crtc_idx);
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priv->crtcs[priv->num_crtcs++] = crtc;
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priv->planes[priv->num_planes++] = plane;
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priv->encoders[priv->num_encoders++] = encoder;
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priv->connectors[priv->num_connectors++] = connector;
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plane_idx++;
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crtc_idx++;
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}
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/*
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* Create normal planes for the remaining overlays:
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*/
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for (; plane_idx < num_ovls; plane_idx++) {
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struct drm_plane *plane;
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if (WARN_ON(priv->num_planes >= ARRAY_SIZE(priv->planes)))
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return -EINVAL;
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plane = omap_plane_init(dev, plane_idx, DRM_PLANE_TYPE_OVERLAY,
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plane_crtc_mask);
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if (IS_ERR(plane))
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return PTR_ERR(plane);
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priv->planes[priv->num_planes++] = plane;
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}
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DBG("registered %d planes, %d crtcs, %d encoders and %d connectors\n",
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priv->num_planes, priv->num_crtcs, priv->num_encoders,
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priv->num_connectors);
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dev->mode_config.min_width = 8;
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dev->mode_config.min_height = 2;
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/*
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* Note: these values are used for multiple independent things:
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* connector mode filtering, buffer sizes, crtc sizes...
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* Use big enough values here to cover all use cases, and do more
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* specific checking in the respective code paths.
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*/
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dev->mode_config.max_width = 8192;
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dev->mode_config.max_height = 8192;
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dev->mode_config.funcs = &omap_mode_config_funcs;
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dev->mode_config.helper_private = &omap_mode_config_helper_funcs;
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drm_mode_config_reset(dev);
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omap_drm_irq_install(dev);
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return 0;
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}
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/*
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* Enable the HPD in external components if supported
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*/
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static void omap_modeset_enable_external_hpd(void)
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{
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struct omap_dss_device *dssdev = NULL;
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for_each_dss_dev(dssdev) {
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if (dssdev->driver->enable_hpd)
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dssdev->driver->enable_hpd(dssdev);
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}
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}
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/*
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* Disable the HPD in external components if supported
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*/
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static void omap_modeset_disable_external_hpd(void)
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{
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struct omap_dss_device *dssdev = NULL;
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for_each_dss_dev(dssdev) {
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if (dssdev->driver->disable_hpd)
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dssdev->driver->disable_hpd(dssdev);
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}
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}
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/*
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* drm ioctl funcs
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*/
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static int ioctl_get_param(struct drm_device *dev, void *data,
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struct drm_file *file_priv)
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{
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struct omap_drm_private *priv = dev->dev_private;
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struct drm_omap_param *args = data;
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DBG("%p: param=%llu", dev, args->param);
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switch (args->param) {
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case OMAP_PARAM_CHIPSET_ID:
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args->value = priv->omaprev;
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break;
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default:
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DBG("unknown parameter %lld", args->param);
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return -EINVAL;
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}
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return 0;
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}
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static int ioctl_set_param(struct drm_device *dev, void *data,
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struct drm_file *file_priv)
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{
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struct drm_omap_param *args = data;
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switch (args->param) {
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default:
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DBG("unknown parameter %lld", args->param);
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return -EINVAL;
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}
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return 0;
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}
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#define OMAP_BO_USER_MASK 0x00ffffff /* flags settable by userspace */
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static int ioctl_gem_new(struct drm_device *dev, void *data,
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struct drm_file *file_priv)
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{
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struct drm_omap_gem_new *args = data;
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u32 flags = args->flags & OMAP_BO_USER_MASK;
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VERB("%p:%p: size=0x%08x, flags=%08x", dev, file_priv,
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args->size.bytes, flags);
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return omap_gem_new_handle(dev, file_priv, args->size, flags,
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&args->handle);
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}
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static int ioctl_gem_info(struct drm_device *dev, void *data,
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struct drm_file *file_priv)
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{
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struct drm_omap_gem_info *args = data;
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struct drm_gem_object *obj;
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int ret = 0;
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VERB("%p:%p: handle=%d", dev, file_priv, args->handle);
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obj = drm_gem_object_lookup(file_priv, args->handle);
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if (!obj)
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return -ENOENT;
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args->size = omap_gem_mmap_size(obj);
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args->offset = omap_gem_mmap_offset(obj);
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drm_gem_object_unreference_unlocked(obj);
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return ret;
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}
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static const struct drm_ioctl_desc ioctls[DRM_COMMAND_END - DRM_COMMAND_BASE] = {
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DRM_IOCTL_DEF_DRV(OMAP_GET_PARAM, ioctl_get_param,
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DRM_AUTH | DRM_RENDER_ALLOW),
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DRM_IOCTL_DEF_DRV(OMAP_SET_PARAM, ioctl_set_param,
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DRM_AUTH | DRM_MASTER | DRM_ROOT_ONLY),
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DRM_IOCTL_DEF_DRV(OMAP_GEM_NEW, ioctl_gem_new,
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DRM_AUTH | DRM_RENDER_ALLOW),
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/* Deprecated, to be removed. */
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DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_PREP, drm_noop,
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DRM_AUTH | DRM_RENDER_ALLOW),
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/* Deprecated, to be removed. */
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DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_FINI, drm_noop,
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DRM_AUTH | DRM_RENDER_ALLOW),
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DRM_IOCTL_DEF_DRV(OMAP_GEM_INFO, ioctl_gem_info,
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DRM_AUTH | DRM_RENDER_ALLOW),
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};
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/*
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* drm driver funcs
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*/
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static int dev_open(struct drm_device *dev, struct drm_file *file)
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{
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file->driver_priv = NULL;
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DBG("open: dev=%p, file=%p", dev, file);
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return 0;
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}
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static const struct vm_operations_struct omap_gem_vm_ops = {
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.fault = omap_gem_fault,
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.open = drm_gem_vm_open,
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.close = drm_gem_vm_close,
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};
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static const struct file_operations omapdriver_fops = {
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.owner = THIS_MODULE,
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.open = drm_open,
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.unlocked_ioctl = drm_ioctl,
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.compat_ioctl = drm_compat_ioctl,
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.release = drm_release,
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.mmap = omap_gem_mmap,
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.poll = drm_poll,
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.read = drm_read,
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.llseek = noop_llseek,
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};
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static struct drm_driver omap_drm_driver = {
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.driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
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DRIVER_ATOMIC | DRIVER_RENDER,
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.open = dev_open,
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.lastclose = drm_fb_helper_lastclose,
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#ifdef CONFIG_DEBUG_FS
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.debugfs_init = omap_debugfs_init,
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#endif
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.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
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.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
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.gem_prime_export = omap_gem_prime_export,
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.gem_prime_import = omap_gem_prime_import,
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.gem_free_object = omap_gem_free_object,
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.gem_vm_ops = &omap_gem_vm_ops,
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.dumb_create = omap_gem_dumb_create,
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.dumb_map_offset = omap_gem_dumb_map_offset,
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.ioctls = ioctls,
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.num_ioctls = DRM_OMAP_NUM_IOCTLS,
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.fops = &omapdriver_fops,
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.name = DRIVER_NAME,
|
|
.desc = DRIVER_DESC,
|
|
.date = DRIVER_DATE,
|
|
.major = DRIVER_MAJOR,
|
|
.minor = DRIVER_MINOR,
|
|
.patchlevel = DRIVER_PATCHLEVEL,
|
|
};
|
|
|
|
static const struct soc_device_attribute omapdrm_soc_devices[] = {
|
|
{ .family = "OMAP3", .data = (void *)0x3430 },
|
|
{ .family = "OMAP4", .data = (void *)0x4430 },
|
|
{ .family = "OMAP5", .data = (void *)0x5430 },
|
|
{ .family = "DRA7", .data = (void *)0x0752 },
|
|
{ /* sentinel */ }
|
|
};
|
|
|
|
static int omapdrm_init(struct omap_drm_private *priv, struct device *dev)
|
|
{
|
|
const struct soc_device_attribute *soc;
|
|
struct drm_device *ddev;
|
|
unsigned int i;
|
|
int ret;
|
|
|
|
DBG("%s", dev_name(dev));
|
|
|
|
priv->dev = dev;
|
|
priv->dss = omapdss_get_dss();
|
|
priv->dispc = dispc_get_dispc(priv->dss);
|
|
priv->dispc_ops = dispc_get_ops(priv->dss);
|
|
|
|
omap_crtc_pre_init(priv);
|
|
|
|
ret = omap_connect_dssdevs();
|
|
if (ret)
|
|
goto err_crtc_uninit;
|
|
|
|
soc = soc_device_match(omapdrm_soc_devices);
|
|
priv->omaprev = soc ? (unsigned int)soc->data : 0;
|
|
priv->wq = alloc_ordered_workqueue("omapdrm", 0);
|
|
|
|
spin_lock_init(&priv->list_lock);
|
|
INIT_LIST_HEAD(&priv->obj_list);
|
|
|
|
/* Allocate and initialize the DRM device. */
|
|
ddev = drm_dev_alloc(&omap_drm_driver, priv->dev);
|
|
if (IS_ERR(ddev)) {
|
|
ret = PTR_ERR(ddev);
|
|
goto err_destroy_wq;
|
|
}
|
|
|
|
priv->ddev = ddev;
|
|
ddev->dev_private = priv;
|
|
|
|
/* Get memory bandwidth limits */
|
|
if (priv->dispc_ops->get_memory_bandwidth_limit)
|
|
priv->max_bandwidth =
|
|
priv->dispc_ops->get_memory_bandwidth_limit(priv->dispc);
|
|
|
|
omap_gem_init(ddev);
|
|
|
|
ret = omap_modeset_init(ddev);
|
|
if (ret) {
|
|
dev_err(priv->dev, "omap_modeset_init failed: ret=%d\n", ret);
|
|
goto err_free_drm_dev;
|
|
}
|
|
|
|
/* Initialize vblank handling, start with all CRTCs disabled. */
|
|
ret = drm_vblank_init(ddev, priv->num_crtcs);
|
|
if (ret) {
|
|
dev_err(priv->dev, "could not init vblank\n");
|
|
goto err_cleanup_modeset;
|
|
}
|
|
|
|
for (i = 0; i < priv->num_crtcs; i++)
|
|
drm_crtc_vblank_off(priv->crtcs[i]);
|
|
|
|
omap_fbdev_init(ddev);
|
|
|
|
drm_kms_helper_poll_init(ddev);
|
|
omap_modeset_enable_external_hpd();
|
|
|
|
/*
|
|
* Register the DRM device with the core and the connectors with
|
|
* sysfs.
|
|
*/
|
|
ret = drm_dev_register(ddev, 0);
|
|
if (ret)
|
|
goto err_cleanup_helpers;
|
|
|
|
return 0;
|
|
|
|
err_cleanup_helpers:
|
|
omap_modeset_disable_external_hpd();
|
|
drm_kms_helper_poll_fini(ddev);
|
|
|
|
omap_fbdev_fini(ddev);
|
|
err_cleanup_modeset:
|
|
drm_mode_config_cleanup(ddev);
|
|
omap_drm_irq_uninstall(ddev);
|
|
err_free_drm_dev:
|
|
omap_gem_deinit(ddev);
|
|
drm_dev_unref(ddev);
|
|
err_destroy_wq:
|
|
destroy_workqueue(priv->wq);
|
|
omap_disconnect_dssdevs();
|
|
err_crtc_uninit:
|
|
omap_crtc_pre_uninit();
|
|
return ret;
|
|
}
|
|
|
|
static void omapdrm_cleanup(struct omap_drm_private *priv)
|
|
{
|
|
struct drm_device *ddev = priv->ddev;
|
|
|
|
DBG("");
|
|
|
|
drm_dev_unregister(ddev);
|
|
|
|
omap_modeset_disable_external_hpd();
|
|
drm_kms_helper_poll_fini(ddev);
|
|
|
|
omap_fbdev_fini(ddev);
|
|
|
|
drm_atomic_helper_shutdown(ddev);
|
|
|
|
drm_mode_config_cleanup(ddev);
|
|
|
|
omap_drm_irq_uninstall(ddev);
|
|
omap_gem_deinit(ddev);
|
|
|
|
drm_dev_unref(ddev);
|
|
|
|
destroy_workqueue(priv->wq);
|
|
|
|
omap_disconnect_dssdevs();
|
|
omap_crtc_pre_uninit();
|
|
}
|
|
|
|
static int pdev_probe(struct platform_device *pdev)
|
|
{
|
|
struct omap_drm_private *priv;
|
|
int ret;
|
|
|
|
if (omapdss_is_initialized() == false)
|
|
return -EPROBE_DEFER;
|
|
|
|
ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed to set the DMA mask\n");
|
|
return ret;
|
|
}
|
|
|
|
/* Allocate and initialize the driver private structure. */
|
|
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
|
|
if (!priv)
|
|
return -ENOMEM;
|
|
|
|
platform_set_drvdata(pdev, priv);
|
|
|
|
ret = omapdrm_init(priv, &pdev->dev);
|
|
if (ret < 0)
|
|
kfree(priv);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int pdev_remove(struct platform_device *pdev)
|
|
{
|
|
struct omap_drm_private *priv = platform_get_drvdata(pdev);
|
|
|
|
omapdrm_cleanup(priv);
|
|
kfree(priv);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int omap_drm_suspend_all_displays(void)
|
|
{
|
|
struct omap_dss_device *dssdev = NULL;
|
|
|
|
for_each_dss_dev(dssdev) {
|
|
if (!dssdev->driver)
|
|
continue;
|
|
|
|
if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
|
|
dssdev->driver->disable(dssdev);
|
|
dssdev->activate_after_resume = true;
|
|
} else {
|
|
dssdev->activate_after_resume = false;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int omap_drm_resume_all_displays(void)
|
|
{
|
|
struct omap_dss_device *dssdev = NULL;
|
|
|
|
for_each_dss_dev(dssdev) {
|
|
if (!dssdev->driver)
|
|
continue;
|
|
|
|
if (dssdev->activate_after_resume) {
|
|
dssdev->driver->enable(dssdev);
|
|
dssdev->activate_after_resume = false;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int omap_drm_suspend(struct device *dev)
|
|
{
|
|
struct omap_drm_private *priv = dev_get_drvdata(dev);
|
|
struct drm_device *drm_dev = priv->ddev;
|
|
|
|
drm_kms_helper_poll_disable(drm_dev);
|
|
|
|
drm_modeset_lock_all(drm_dev);
|
|
omap_drm_suspend_all_displays();
|
|
drm_modeset_unlock_all(drm_dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int omap_drm_resume(struct device *dev)
|
|
{
|
|
struct omap_drm_private *priv = dev_get_drvdata(dev);
|
|
struct drm_device *drm_dev = priv->ddev;
|
|
|
|
drm_modeset_lock_all(drm_dev);
|
|
omap_drm_resume_all_displays();
|
|
drm_modeset_unlock_all(drm_dev);
|
|
|
|
drm_kms_helper_poll_enable(drm_dev);
|
|
|
|
return omap_gem_resume(drm_dev);
|
|
}
|
|
#endif
|
|
|
|
static SIMPLE_DEV_PM_OPS(omapdrm_pm_ops, omap_drm_suspend, omap_drm_resume);
|
|
|
|
static struct platform_driver pdev = {
|
|
.driver = {
|
|
.name = "omapdrm",
|
|
.pm = &omapdrm_pm_ops,
|
|
},
|
|
.probe = pdev_probe,
|
|
.remove = pdev_remove,
|
|
};
|
|
|
|
static struct platform_driver * const drivers[] = {
|
|
&omap_dmm_driver,
|
|
&pdev,
|
|
};
|
|
|
|
static int __init omap_drm_init(void)
|
|
{
|
|
DBG("init");
|
|
|
|
return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
|
|
}
|
|
|
|
static void __exit omap_drm_fini(void)
|
|
{
|
|
DBG("fini");
|
|
|
|
platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
|
|
}
|
|
|
|
/* need late_initcall() so we load after dss_driver's are loaded */
|
|
late_initcall(omap_drm_init);
|
|
module_exit(omap_drm_fini);
|
|
|
|
MODULE_AUTHOR("Rob Clark <rob@ti.com>");
|
|
MODULE_DESCRIPTION("OMAP DRM Display Driver");
|
|
MODULE_ALIAS("platform:" DRIVER_NAME);
|
|
MODULE_LICENSE("GPL v2");
|