![Kent Russell](/assets/img/avatar_default.png)
Change "prefered" to "preferred" Signed-off-by: Kent Russell <kent.russell@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
878 lines
23 KiB
C
878 lines
23 KiB
C
/*
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* Copyright 2008 Jerome Glisse.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Jerome Glisse <glisse@freedesktop.org>
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*/
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#include <linux/list_sort.h>
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#include <drm/drmP.h>
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#include <drm/radeon_drm.h>
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#include "radeon_reg.h"
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#include "radeon.h"
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#include "radeon_trace.h"
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#define RADEON_CS_MAX_PRIORITY 32u
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#define RADEON_CS_NUM_BUCKETS (RADEON_CS_MAX_PRIORITY + 1)
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/* This is based on the bucket sort with O(n) time complexity.
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* An item with priority "i" is added to bucket[i]. The lists are then
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* concatenated in descending order.
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*/
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struct radeon_cs_buckets {
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struct list_head bucket[RADEON_CS_NUM_BUCKETS];
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};
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static void radeon_cs_buckets_init(struct radeon_cs_buckets *b)
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{
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unsigned i;
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for (i = 0; i < RADEON_CS_NUM_BUCKETS; i++)
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INIT_LIST_HEAD(&b->bucket[i]);
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}
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static void radeon_cs_buckets_add(struct radeon_cs_buckets *b,
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struct list_head *item, unsigned priority)
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{
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/* Since buffers which appear sooner in the relocation list are
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* likely to be used more often than buffers which appear later
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* in the list, the sort mustn't change the ordering of buffers
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* with the same priority, i.e. it must be stable.
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*/
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list_add_tail(item, &b->bucket[min(priority, RADEON_CS_MAX_PRIORITY)]);
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}
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static void radeon_cs_buckets_get_list(struct radeon_cs_buckets *b,
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struct list_head *out_list)
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{
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unsigned i;
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/* Connect the sorted buckets in the output list. */
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for (i = 0; i < RADEON_CS_NUM_BUCKETS; i++) {
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list_splice(&b->bucket[i], out_list);
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}
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}
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static int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
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{
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struct radeon_cs_chunk *chunk;
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struct radeon_cs_buckets buckets;
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unsigned i;
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bool need_mmap_lock = false;
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int r;
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if (p->chunk_relocs == NULL) {
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return 0;
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}
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chunk = p->chunk_relocs;
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p->dma_reloc_idx = 0;
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/* FIXME: we assume that each relocs use 4 dwords */
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p->nrelocs = chunk->length_dw / 4;
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p->relocs = kvmalloc_array(p->nrelocs, sizeof(struct radeon_bo_list),
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GFP_KERNEL | __GFP_ZERO);
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if (p->relocs == NULL) {
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return -ENOMEM;
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}
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radeon_cs_buckets_init(&buckets);
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for (i = 0; i < p->nrelocs; i++) {
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struct drm_radeon_cs_reloc *r;
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struct drm_gem_object *gobj;
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unsigned priority;
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r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4];
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gobj = drm_gem_object_lookup(p->filp, r->handle);
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if (gobj == NULL) {
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DRM_ERROR("gem object lookup failed 0x%x\n",
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r->handle);
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return -ENOENT;
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}
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p->relocs[i].robj = gem_to_radeon_bo(gobj);
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/* The userspace buffer priorities are from 0 to 15. A higher
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* number means the buffer is more important.
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* Also, the buffers used for write have a higher priority than
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* the buffers used for read only, which doubles the range
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* to 0 to 31. 32 is reserved for the kernel driver.
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*/
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priority = (r->flags & RADEON_RELOC_PRIO_MASK) * 2
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+ !!r->write_domain;
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/* The first reloc of an UVD job is the msg and that must be in
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* VRAM, the second reloc is the DPB and for WMV that must be in
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* VRAM as well. Also put everything into VRAM on AGP cards and older
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* IGP chips to avoid image corruptions
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*/
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if (p->ring == R600_RING_TYPE_UVD_INDEX &&
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(i <= 0 || pci_find_capability(p->rdev->ddev->pdev,
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PCI_CAP_ID_AGP) ||
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p->rdev->family == CHIP_RS780 ||
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p->rdev->family == CHIP_RS880)) {
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/* TODO: is this still needed for NI+ ? */
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p->relocs[i].preferred_domains =
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RADEON_GEM_DOMAIN_VRAM;
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p->relocs[i].allowed_domains =
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RADEON_GEM_DOMAIN_VRAM;
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/* prioritize this over any other relocation */
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priority = RADEON_CS_MAX_PRIORITY;
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} else {
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uint32_t domain = r->write_domain ?
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r->write_domain : r->read_domains;
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if (domain & RADEON_GEM_DOMAIN_CPU) {
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DRM_ERROR("RADEON_GEM_DOMAIN_CPU is not valid "
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"for command submission\n");
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return -EINVAL;
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}
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p->relocs[i].preferred_domains = domain;
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if (domain == RADEON_GEM_DOMAIN_VRAM)
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domain |= RADEON_GEM_DOMAIN_GTT;
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p->relocs[i].allowed_domains = domain;
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}
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if (radeon_ttm_tt_has_userptr(p->relocs[i].robj->tbo.ttm)) {
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uint32_t domain = p->relocs[i].preferred_domains;
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if (!(domain & RADEON_GEM_DOMAIN_GTT)) {
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DRM_ERROR("Only RADEON_GEM_DOMAIN_GTT is "
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"allowed for userptr BOs\n");
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return -EINVAL;
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}
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need_mmap_lock = true;
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domain = RADEON_GEM_DOMAIN_GTT;
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p->relocs[i].preferred_domains = domain;
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p->relocs[i].allowed_domains = domain;
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}
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/* Objects shared as dma-bufs cannot be moved to VRAM */
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if (p->relocs[i].robj->prime_shared_count) {
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p->relocs[i].allowed_domains &= ~RADEON_GEM_DOMAIN_VRAM;
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if (!p->relocs[i].allowed_domains) {
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DRM_ERROR("BO associated with dma-buf cannot "
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"be moved to VRAM\n");
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return -EINVAL;
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}
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}
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p->relocs[i].tv.bo = &p->relocs[i].robj->tbo;
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p->relocs[i].tv.shared = !r->write_domain;
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radeon_cs_buckets_add(&buckets, &p->relocs[i].tv.head,
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priority);
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}
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radeon_cs_buckets_get_list(&buckets, &p->validated);
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if (p->cs_flags & RADEON_CS_USE_VM)
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p->vm_bos = radeon_vm_get_bos(p->rdev, p->ib.vm,
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&p->validated);
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if (need_mmap_lock)
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down_read(¤t->mm->mmap_sem);
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r = radeon_bo_list_validate(p->rdev, &p->ticket, &p->validated, p->ring);
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if (need_mmap_lock)
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up_read(¤t->mm->mmap_sem);
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return r;
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}
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static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)
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{
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p->priority = priority;
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switch (ring) {
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default:
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DRM_ERROR("unknown ring id: %d\n", ring);
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return -EINVAL;
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case RADEON_CS_RING_GFX:
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p->ring = RADEON_RING_TYPE_GFX_INDEX;
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break;
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case RADEON_CS_RING_COMPUTE:
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if (p->rdev->family >= CHIP_TAHITI) {
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if (p->priority > 0)
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p->ring = CAYMAN_RING_TYPE_CP1_INDEX;
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else
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p->ring = CAYMAN_RING_TYPE_CP2_INDEX;
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} else
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p->ring = RADEON_RING_TYPE_GFX_INDEX;
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break;
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case RADEON_CS_RING_DMA:
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if (p->rdev->family >= CHIP_CAYMAN) {
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if (p->priority > 0)
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p->ring = R600_RING_TYPE_DMA_INDEX;
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else
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p->ring = CAYMAN_RING_TYPE_DMA1_INDEX;
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} else if (p->rdev->family >= CHIP_RV770) {
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p->ring = R600_RING_TYPE_DMA_INDEX;
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} else {
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return -EINVAL;
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}
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break;
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case RADEON_CS_RING_UVD:
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p->ring = R600_RING_TYPE_UVD_INDEX;
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break;
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case RADEON_CS_RING_VCE:
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/* TODO: only use the low priority ring for now */
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p->ring = TN_RING_TYPE_VCE1_INDEX;
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break;
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}
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return 0;
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}
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static int radeon_cs_sync_rings(struct radeon_cs_parser *p)
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{
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struct radeon_bo_list *reloc;
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int r;
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list_for_each_entry(reloc, &p->validated, tv.head) {
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struct reservation_object *resv;
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resv = reloc->robj->tbo.resv;
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r = radeon_sync_resv(p->rdev, &p->ib.sync, resv,
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reloc->tv.shared);
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if (r)
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return r;
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}
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return 0;
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}
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/* XXX: note that this is called from the legacy UMS CS ioctl as well */
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int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
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{
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struct drm_radeon_cs *cs = data;
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uint64_t *chunk_array_ptr;
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unsigned size, i;
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u32 ring = RADEON_CS_RING_GFX;
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s32 priority = 0;
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INIT_LIST_HEAD(&p->validated);
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if (!cs->num_chunks) {
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return 0;
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}
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/* get chunks */
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p->idx = 0;
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p->ib.sa_bo = NULL;
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p->const_ib.sa_bo = NULL;
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p->chunk_ib = NULL;
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p->chunk_relocs = NULL;
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p->chunk_flags = NULL;
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p->chunk_const_ib = NULL;
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p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL);
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if (p->chunks_array == NULL) {
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return -ENOMEM;
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}
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chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);
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if (copy_from_user(p->chunks_array, chunk_array_ptr,
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sizeof(uint64_t)*cs->num_chunks)) {
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return -EFAULT;
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}
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p->cs_flags = 0;
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p->nchunks = cs->num_chunks;
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p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL);
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if (p->chunks == NULL) {
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return -ENOMEM;
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}
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for (i = 0; i < p->nchunks; i++) {
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struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
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struct drm_radeon_cs_chunk user_chunk;
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uint32_t __user *cdata;
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chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i];
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if (copy_from_user(&user_chunk, chunk_ptr,
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sizeof(struct drm_radeon_cs_chunk))) {
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return -EFAULT;
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}
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p->chunks[i].length_dw = user_chunk.length_dw;
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if (user_chunk.chunk_id == RADEON_CHUNK_ID_RELOCS) {
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p->chunk_relocs = &p->chunks[i];
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}
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if (user_chunk.chunk_id == RADEON_CHUNK_ID_IB) {
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p->chunk_ib = &p->chunks[i];
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/* zero length IB isn't useful */
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if (p->chunks[i].length_dw == 0)
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return -EINVAL;
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}
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if (user_chunk.chunk_id == RADEON_CHUNK_ID_CONST_IB) {
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p->chunk_const_ib = &p->chunks[i];
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/* zero length CONST IB isn't useful */
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if (p->chunks[i].length_dw == 0)
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return -EINVAL;
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}
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if (user_chunk.chunk_id == RADEON_CHUNK_ID_FLAGS) {
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p->chunk_flags = &p->chunks[i];
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/* zero length flags aren't useful */
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if (p->chunks[i].length_dw == 0)
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return -EINVAL;
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}
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size = p->chunks[i].length_dw;
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cdata = (void __user *)(unsigned long)user_chunk.chunk_data;
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p->chunks[i].user_ptr = cdata;
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if (user_chunk.chunk_id == RADEON_CHUNK_ID_CONST_IB)
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continue;
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if (user_chunk.chunk_id == RADEON_CHUNK_ID_IB) {
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if (!p->rdev || !(p->rdev->flags & RADEON_IS_AGP))
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continue;
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}
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p->chunks[i].kdata = kvmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);
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size *= sizeof(uint32_t);
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if (p->chunks[i].kdata == NULL) {
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return -ENOMEM;
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}
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if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
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return -EFAULT;
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}
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if (user_chunk.chunk_id == RADEON_CHUNK_ID_FLAGS) {
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p->cs_flags = p->chunks[i].kdata[0];
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if (p->chunks[i].length_dw > 1)
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ring = p->chunks[i].kdata[1];
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if (p->chunks[i].length_dw > 2)
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priority = (s32)p->chunks[i].kdata[2];
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}
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}
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/* these are KMS only */
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if (p->rdev) {
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if ((p->cs_flags & RADEON_CS_USE_VM) &&
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!p->rdev->vm_manager.enabled) {
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DRM_ERROR("VM not active on asic!\n");
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return -EINVAL;
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}
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if (radeon_cs_get_ring(p, ring, priority))
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return -EINVAL;
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/* we only support VM on some SI+ rings */
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if ((p->cs_flags & RADEON_CS_USE_VM) == 0) {
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if (p->rdev->asic->ring[p->ring]->cs_parse == NULL) {
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DRM_ERROR("Ring %d requires VM!\n", p->ring);
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return -EINVAL;
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}
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} else {
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if (p->rdev->asic->ring[p->ring]->ib_parse == NULL) {
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DRM_ERROR("VM not supported on ring %d!\n",
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p->ring);
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return -EINVAL;
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}
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}
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}
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return 0;
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}
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static int cmp_size_smaller_first(void *priv, struct list_head *a,
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struct list_head *b)
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{
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struct radeon_bo_list *la = list_entry(a, struct radeon_bo_list, tv.head);
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struct radeon_bo_list *lb = list_entry(b, struct radeon_bo_list, tv.head);
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/* Sort A before B if A is smaller. */
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return (int)la->robj->tbo.num_pages - (int)lb->robj->tbo.num_pages;
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}
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/**
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* cs_parser_fini() - clean parser states
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* @parser: parser structure holding parsing context.
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* @error: error number
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*
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* If error is set than unvalidate buffer, otherwise just free memory
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* used by parsing context.
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**/
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static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error, bool backoff)
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{
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unsigned i;
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if (!error) {
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/* Sort the buffer list from the smallest to largest buffer,
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* which affects the order of buffers in the LRU list.
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* This assures that the smallest buffers are added first
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* to the LRU list, so they are likely to be later evicted
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* first, instead of large buffers whose eviction is more
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* expensive.
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*
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* This slightly lowers the number of bytes moved by TTM
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* per frame under memory pressure.
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*/
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list_sort(NULL, &parser->validated, cmp_size_smaller_first);
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ttm_eu_fence_buffer_objects(&parser->ticket,
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&parser->validated,
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&parser->ib.fence->base);
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} else if (backoff) {
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ttm_eu_backoff_reservation(&parser->ticket,
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&parser->validated);
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}
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if (parser->relocs != NULL) {
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for (i = 0; i < parser->nrelocs; i++) {
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struct radeon_bo *bo = parser->relocs[i].robj;
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if (bo == NULL)
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continue;
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drm_gem_object_put_unlocked(&bo->gem_base);
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}
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}
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kfree(parser->track);
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kvfree(parser->relocs);
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kvfree(parser->vm_bos);
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for (i = 0; i < parser->nchunks; i++)
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kvfree(parser->chunks[i].kdata);
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kfree(parser->chunks);
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kfree(parser->chunks_array);
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radeon_ib_free(parser->rdev, &parser->ib);
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radeon_ib_free(parser->rdev, &parser->const_ib);
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}
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static int radeon_cs_ib_chunk(struct radeon_device *rdev,
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struct radeon_cs_parser *parser)
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{
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int r;
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if (parser->chunk_ib == NULL)
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return 0;
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if (parser->cs_flags & RADEON_CS_USE_VM)
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return 0;
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r = radeon_cs_parse(rdev, parser->ring, parser);
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if (r || parser->parser_error) {
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|
DRM_ERROR("Invalid command stream !\n");
|
|
return r;
|
|
}
|
|
|
|
r = radeon_cs_sync_rings(parser);
|
|
if (r) {
|
|
if (r != -ERESTARTSYS)
|
|
DRM_ERROR("Failed to sync rings: %i\n", r);
|
|
return r;
|
|
}
|
|
|
|
if (parser->ring == R600_RING_TYPE_UVD_INDEX)
|
|
radeon_uvd_note_usage(rdev);
|
|
else if ((parser->ring == TN_RING_TYPE_VCE1_INDEX) ||
|
|
(parser->ring == TN_RING_TYPE_VCE2_INDEX))
|
|
radeon_vce_note_usage(rdev);
|
|
|
|
r = radeon_ib_schedule(rdev, &parser->ib, NULL, true);
|
|
if (r) {
|
|
DRM_ERROR("Failed to schedule IB !\n");
|
|
}
|
|
return r;
|
|
}
|
|
|
|
static int radeon_bo_vm_update_pte(struct radeon_cs_parser *p,
|
|
struct radeon_vm *vm)
|
|
{
|
|
struct radeon_device *rdev = p->rdev;
|
|
struct radeon_bo_va *bo_va;
|
|
int i, r;
|
|
|
|
r = radeon_vm_update_page_directory(rdev, vm);
|
|
if (r)
|
|
return r;
|
|
|
|
r = radeon_vm_clear_freed(rdev, vm);
|
|
if (r)
|
|
return r;
|
|
|
|
if (vm->ib_bo_va == NULL) {
|
|
DRM_ERROR("Tmp BO not in VM!\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
r = radeon_vm_bo_update(rdev, vm->ib_bo_va,
|
|
&rdev->ring_tmp_bo.bo->tbo.mem);
|
|
if (r)
|
|
return r;
|
|
|
|
for (i = 0; i < p->nrelocs; i++) {
|
|
struct radeon_bo *bo;
|
|
|
|
bo = p->relocs[i].robj;
|
|
bo_va = radeon_vm_bo_find(vm, bo);
|
|
if (bo_va == NULL) {
|
|
dev_err(rdev->dev, "bo %p not in vm %p\n", bo, vm);
|
|
return -EINVAL;
|
|
}
|
|
|
|
r = radeon_vm_bo_update(rdev, bo_va, &bo->tbo.mem);
|
|
if (r)
|
|
return r;
|
|
|
|
radeon_sync_fence(&p->ib.sync, bo_va->last_pt_update);
|
|
}
|
|
|
|
return radeon_vm_clear_invalids(rdev, vm);
|
|
}
|
|
|
|
static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
|
|
struct radeon_cs_parser *parser)
|
|
{
|
|
struct radeon_fpriv *fpriv = parser->filp->driver_priv;
|
|
struct radeon_vm *vm = &fpriv->vm;
|
|
int r;
|
|
|
|
if (parser->chunk_ib == NULL)
|
|
return 0;
|
|
if ((parser->cs_flags & RADEON_CS_USE_VM) == 0)
|
|
return 0;
|
|
|
|
if (parser->const_ib.length_dw) {
|
|
r = radeon_ring_ib_parse(rdev, parser->ring, &parser->const_ib);
|
|
if (r) {
|
|
return r;
|
|
}
|
|
}
|
|
|
|
r = radeon_ring_ib_parse(rdev, parser->ring, &parser->ib);
|
|
if (r) {
|
|
return r;
|
|
}
|
|
|
|
if (parser->ring == R600_RING_TYPE_UVD_INDEX)
|
|
radeon_uvd_note_usage(rdev);
|
|
|
|
mutex_lock(&vm->mutex);
|
|
r = radeon_bo_vm_update_pte(parser, vm);
|
|
if (r) {
|
|
goto out;
|
|
}
|
|
|
|
r = radeon_cs_sync_rings(parser);
|
|
if (r) {
|
|
if (r != -ERESTARTSYS)
|
|
DRM_ERROR("Failed to sync rings: %i\n", r);
|
|
goto out;
|
|
}
|
|
|
|
if ((rdev->family >= CHIP_TAHITI) &&
|
|
(parser->chunk_const_ib != NULL)) {
|
|
r = radeon_ib_schedule(rdev, &parser->ib, &parser->const_ib, true);
|
|
} else {
|
|
r = radeon_ib_schedule(rdev, &parser->ib, NULL, true);
|
|
}
|
|
|
|
out:
|
|
mutex_unlock(&vm->mutex);
|
|
return r;
|
|
}
|
|
|
|
static int radeon_cs_handle_lockup(struct radeon_device *rdev, int r)
|
|
{
|
|
if (r == -EDEADLK) {
|
|
r = radeon_gpu_reset(rdev);
|
|
if (!r)
|
|
r = -EAGAIN;
|
|
}
|
|
return r;
|
|
}
|
|
|
|
static int radeon_cs_ib_fill(struct radeon_device *rdev, struct radeon_cs_parser *parser)
|
|
{
|
|
struct radeon_cs_chunk *ib_chunk;
|
|
struct radeon_vm *vm = NULL;
|
|
int r;
|
|
|
|
if (parser->chunk_ib == NULL)
|
|
return 0;
|
|
|
|
if (parser->cs_flags & RADEON_CS_USE_VM) {
|
|
struct radeon_fpriv *fpriv = parser->filp->driver_priv;
|
|
vm = &fpriv->vm;
|
|
|
|
if ((rdev->family >= CHIP_TAHITI) &&
|
|
(parser->chunk_const_ib != NULL)) {
|
|
ib_chunk = parser->chunk_const_ib;
|
|
if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
|
|
DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw);
|
|
return -EINVAL;
|
|
}
|
|
r = radeon_ib_get(rdev, parser->ring, &parser->const_ib,
|
|
vm, ib_chunk->length_dw * 4);
|
|
if (r) {
|
|
DRM_ERROR("Failed to get const ib !\n");
|
|
return r;
|
|
}
|
|
parser->const_ib.is_const_ib = true;
|
|
parser->const_ib.length_dw = ib_chunk->length_dw;
|
|
if (copy_from_user(parser->const_ib.ptr,
|
|
ib_chunk->user_ptr,
|
|
ib_chunk->length_dw * 4))
|
|
return -EFAULT;
|
|
}
|
|
|
|
ib_chunk = parser->chunk_ib;
|
|
if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
|
|
DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw);
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
ib_chunk = parser->chunk_ib;
|
|
|
|
r = radeon_ib_get(rdev, parser->ring, &parser->ib,
|
|
vm, ib_chunk->length_dw * 4);
|
|
if (r) {
|
|
DRM_ERROR("Failed to get ib !\n");
|
|
return r;
|
|
}
|
|
parser->ib.length_dw = ib_chunk->length_dw;
|
|
if (ib_chunk->kdata)
|
|
memcpy(parser->ib.ptr, ib_chunk->kdata, ib_chunk->length_dw * 4);
|
|
else if (copy_from_user(parser->ib.ptr, ib_chunk->user_ptr, ib_chunk->length_dw * 4))
|
|
return -EFAULT;
|
|
return 0;
|
|
}
|
|
|
|
int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
|
|
{
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
struct radeon_cs_parser parser;
|
|
int r;
|
|
|
|
down_read(&rdev->exclusive_lock);
|
|
if (!rdev->accel_working) {
|
|
up_read(&rdev->exclusive_lock);
|
|
return -EBUSY;
|
|
}
|
|
if (rdev->in_reset) {
|
|
up_read(&rdev->exclusive_lock);
|
|
r = radeon_gpu_reset(rdev);
|
|
if (!r)
|
|
r = -EAGAIN;
|
|
return r;
|
|
}
|
|
/* initialize parser */
|
|
memset(&parser, 0, sizeof(struct radeon_cs_parser));
|
|
parser.filp = filp;
|
|
parser.rdev = rdev;
|
|
parser.dev = rdev->dev;
|
|
parser.family = rdev->family;
|
|
r = radeon_cs_parser_init(&parser, data);
|
|
if (r) {
|
|
DRM_ERROR("Failed to initialize parser !\n");
|
|
radeon_cs_parser_fini(&parser, r, false);
|
|
up_read(&rdev->exclusive_lock);
|
|
r = radeon_cs_handle_lockup(rdev, r);
|
|
return r;
|
|
}
|
|
|
|
r = radeon_cs_ib_fill(rdev, &parser);
|
|
if (!r) {
|
|
r = radeon_cs_parser_relocs(&parser);
|
|
if (r && r != -ERESTARTSYS)
|
|
DRM_ERROR("Failed to parse relocation %d!\n", r);
|
|
}
|
|
|
|
if (r) {
|
|
radeon_cs_parser_fini(&parser, r, false);
|
|
up_read(&rdev->exclusive_lock);
|
|
r = radeon_cs_handle_lockup(rdev, r);
|
|
return r;
|
|
}
|
|
|
|
trace_radeon_cs(&parser);
|
|
|
|
r = radeon_cs_ib_chunk(rdev, &parser);
|
|
if (r) {
|
|
goto out;
|
|
}
|
|
r = radeon_cs_ib_vm_chunk(rdev, &parser);
|
|
if (r) {
|
|
goto out;
|
|
}
|
|
out:
|
|
radeon_cs_parser_fini(&parser, r, true);
|
|
up_read(&rdev->exclusive_lock);
|
|
r = radeon_cs_handle_lockup(rdev, r);
|
|
return r;
|
|
}
|
|
|
|
/**
|
|
* radeon_cs_packet_parse() - parse cp packet and point ib index to next packet
|
|
* @parser: parser structure holding parsing context.
|
|
* @pkt: where to store packet information
|
|
*
|
|
* Assume that chunk_ib_index is properly set. Will return -EINVAL
|
|
* if packet is bigger than remaining ib size. or if packets is unknown.
|
|
**/
|
|
int radeon_cs_packet_parse(struct radeon_cs_parser *p,
|
|
struct radeon_cs_packet *pkt,
|
|
unsigned idx)
|
|
{
|
|
struct radeon_cs_chunk *ib_chunk = p->chunk_ib;
|
|
struct radeon_device *rdev = p->rdev;
|
|
uint32_t header;
|
|
int ret = 0, i;
|
|
|
|
if (idx >= ib_chunk->length_dw) {
|
|
DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
|
|
idx, ib_chunk->length_dw);
|
|
return -EINVAL;
|
|
}
|
|
header = radeon_get_ib_value(p, idx);
|
|
pkt->idx = idx;
|
|
pkt->type = RADEON_CP_PACKET_GET_TYPE(header);
|
|
pkt->count = RADEON_CP_PACKET_GET_COUNT(header);
|
|
pkt->one_reg_wr = 0;
|
|
switch (pkt->type) {
|
|
case RADEON_PACKET_TYPE0:
|
|
if (rdev->family < CHIP_R600) {
|
|
pkt->reg = R100_CP_PACKET0_GET_REG(header);
|
|
pkt->one_reg_wr =
|
|
RADEON_CP_PACKET0_GET_ONE_REG_WR(header);
|
|
} else
|
|
pkt->reg = R600_CP_PACKET0_GET_REG(header);
|
|
break;
|
|
case RADEON_PACKET_TYPE3:
|
|
pkt->opcode = RADEON_CP_PACKET3_GET_OPCODE(header);
|
|
break;
|
|
case RADEON_PACKET_TYPE2:
|
|
pkt->count = -1;
|
|
break;
|
|
default:
|
|
DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
|
|
ret = -EINVAL;
|
|
goto dump_ib;
|
|
}
|
|
if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
|
|
DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
|
|
pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
|
|
ret = -EINVAL;
|
|
goto dump_ib;
|
|
}
|
|
return 0;
|
|
|
|
dump_ib:
|
|
for (i = 0; i < ib_chunk->length_dw; i++) {
|
|
if (i == idx)
|
|
printk("\t0x%08x <---\n", radeon_get_ib_value(p, i));
|
|
else
|
|
printk("\t0x%08x\n", radeon_get_ib_value(p, i));
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* radeon_cs_packet_next_is_pkt3_nop() - test if the next packet is P3 NOP
|
|
* @p: structure holding the parser context.
|
|
*
|
|
* Check if the next packet is NOP relocation packet3.
|
|
**/
|
|
bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
|
|
{
|
|
struct radeon_cs_packet p3reloc;
|
|
int r;
|
|
|
|
r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
|
|
if (r)
|
|
return false;
|
|
if (p3reloc.type != RADEON_PACKET_TYPE3)
|
|
return false;
|
|
if (p3reloc.opcode != RADEON_PACKET3_NOP)
|
|
return false;
|
|
return true;
|
|
}
|
|
|
|
/**
|
|
* radeon_cs_dump_packet() - dump raw packet context
|
|
* @p: structure holding the parser context.
|
|
* @pkt: structure holding the packet.
|
|
*
|
|
* Used mostly for debugging and error reporting.
|
|
**/
|
|
void radeon_cs_dump_packet(struct radeon_cs_parser *p,
|
|
struct radeon_cs_packet *pkt)
|
|
{
|
|
volatile uint32_t *ib;
|
|
unsigned i;
|
|
unsigned idx;
|
|
|
|
ib = p->ib.ptr;
|
|
idx = pkt->idx;
|
|
for (i = 0; i <= (pkt->count + 1); i++, idx++)
|
|
DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
|
|
}
|
|
|
|
/**
|
|
* radeon_cs_packet_next_reloc() - parse next (should be reloc) packet
|
|
* @parser: parser structure holding parsing context.
|
|
* @data: pointer to relocation data
|
|
* @offset_start: starting offset
|
|
* @offset_mask: offset mask (to align start offset on)
|
|
* @reloc: reloc informations
|
|
*
|
|
* Check if next packet is relocation packet3, do bo validation and compute
|
|
* GPU offset using the provided start.
|
|
**/
|
|
int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
|
|
struct radeon_bo_list **cs_reloc,
|
|
int nomm)
|
|
{
|
|
struct radeon_cs_chunk *relocs_chunk;
|
|
struct radeon_cs_packet p3reloc;
|
|
unsigned idx;
|
|
int r;
|
|
|
|
if (p->chunk_relocs == NULL) {
|
|
DRM_ERROR("No relocation chunk !\n");
|
|
return -EINVAL;
|
|
}
|
|
*cs_reloc = NULL;
|
|
relocs_chunk = p->chunk_relocs;
|
|
r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
|
|
if (r)
|
|
return r;
|
|
p->idx += p3reloc.count + 2;
|
|
if (p3reloc.type != RADEON_PACKET_TYPE3 ||
|
|
p3reloc.opcode != RADEON_PACKET3_NOP) {
|
|
DRM_ERROR("No packet3 for relocation for packet at %d.\n",
|
|
p3reloc.idx);
|
|
radeon_cs_dump_packet(p, &p3reloc);
|
|
return -EINVAL;
|
|
}
|
|
idx = radeon_get_ib_value(p, p3reloc.idx + 1);
|
|
if (idx >= relocs_chunk->length_dw) {
|
|
DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
|
|
idx, relocs_chunk->length_dw);
|
|
radeon_cs_dump_packet(p, &p3reloc);
|
|
return -EINVAL;
|
|
}
|
|
/* FIXME: we assume reloc size is 4 dwords */
|
|
if (nomm) {
|
|
*cs_reloc = p->relocs;
|
|
(*cs_reloc)->gpu_offset =
|
|
(u64)relocs_chunk->kdata[idx + 3] << 32;
|
|
(*cs_reloc)->gpu_offset |= relocs_chunk->kdata[idx + 0];
|
|
} else
|
|
*cs_reloc = &p->relocs[(idx / 4)];
|
|
return 0;
|
|
}
|