![Lukas Wunner](/assets/img/avatar_default.png)
Back in 2013, runtime PM for GPUs with integrated HDA controller was introduced with commits0d69704ae3
("gpu/vga_switcheroo: add driver control power feature. (v3)") and246efa4a07
("snd/hda: add runtime suspend/resume on optimus support (v4)"). Briefly, the idea was that the HDA controller is forced on and off in unison with the GPU. The original code is mostly still in place even though it was never a 100% perfect solution: E.g. on access to the HDA controller, the GPU is powered up via vga_switcheroo_runtime_resume_hdmi_audio() but there are no provisions to keep it resumed until access to the HDA controller has ceased: The GPU autosuspends after 5 seconds, rendering the HDA controller inaccessible. Additionally, a kludge is required when hda_intel.c probes: It has to check whether the GPU is powered down (check_hdmi_disabled()) and defer probing if so. However in the meantime (in v4.10) the driver core has gained a feature called device links which promises to solve such issues in a clean way: It allows us to declare a dependency from the HDA controller (consumer) to the GPU (supplier). The PM core then automagically ensures that the GPU is runtime resumed as long as the HDA controller's ->probe hook is executed and whenever the HDA controller is accessed. By default, the HDA controller has a dependency on its parent, a PCIe Root Port. Adding a device link creates another dependency on its sibling: PCIe Root Port ^ ^ | | | | HDA ===> GPU The device link is not only used for runtime PM, it also guarantees that on system sleep, the HDA controller suspends before the GPU and resumes after the GPU, and on system shutdown the HDA controller's ->shutdown hook is executed before the one of the GPU. It is a complete solution. Using this functionality is as simple as calling device_link_add(), which results in a dmesg entry like this: pci 0000:01:00.1: Linked as a consumer to 0000:01:00.0 The code for the GPU-governed audio power management can thus be removed (except where it's still needed for legacy manual power control). The device link is added in a PCI quirk rather than in hda_intel.c. It is therefore legal for the GPU to runtime suspend to D3cold even if the HDA controller is not bound to a driver or if CONFIG_SND_HDA_INTEL is not enabled, for accesses to the HDA controller will cause the GPU to wake up regardless if they're occurring outside of hda_intel.c (think config space readout via sysfs). Contrary to the previous implementation, the HDA controller's power state is now self-governed, rather than GPU-governed, whereas the GPU's power state is no longer fully self-governed. (The HDA controller needs to runtime suspend before the GPU can.) It is thus crucial that runtime PM is always activated on the HDA controller even if CONFIG_SND_HDA_POWER_SAVE_DEFAULT is set to 0 (which is the default), lest the GPU stays awake. This is achieved by setting the auto_runtime_pm flag on every codec and the AZX_DCAPS_PM_RUNTIME flag on the HDA controller. A side effect is that power consumption might be reduced if the GPU is in use but the HDA controller is not, because the HDA controller is now allowed to go to D3hot. Before, it was forced to stay in D0 as long as the GPU was in use. (There is no reduction in power consumption on my Nvidia GK107, but there might be on other chips.) The code paths for legacy manual power control are adjusted such that runtime PM is disabled during power off, thereby preventing the PM core from resuming the HDA controller. Note that the device link is not only added on vga_switcheroo capable systems, but for *any* GPU with integrated HDA controller. The idea is that the HDA controller streams audio via connectors located on the GPU, so the GPU needs to be on for the HDA controller to do anything useful. This commit implicitly fixes an unbalanced runtime PM ref upon unbind of hda_intel.c: On ->probe, a runtime PM ref was previously released under the condition "azx_has_pm_runtime(chip) || hda->use_vga_switcheroo", but on ->remove a runtime PM ref was only acquired under the first of those conditions. Thus, binding and unbinding the driver twice on a vga_switcheroo capable system caused the runtime PM refcount to drop below zero. The issue is resolved because the AZX_DCAPS_PM_RUNTIME flag is now always set if use_vga_switcheroo is true. For more information on device links please refer to: https://www.kernel.org/doc/html/latest/driver-api/device_link.html Documentation/driver-api/device_link.rst Cc: Dave Airlie <airlied@redhat.com> Cc: Ben Skeggs <bskeggs@redhat.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Takashi Iwai <tiwai@suse.de> Reviewed-by: Peter Wu <peter@lekensteyn.nl> Tested-by: Kai Heng Feng <kai.heng.feng@canonical.com> # AMD PowerXpress Tested-by: Mike Lothian <mike@fireburn.co.uk> # AMD PowerXpress Tested-by: Denis Lisov <dennis.lissov@gmail.com> # Nvidia Optimus Tested-by: Peter Wu <peter@lekensteyn.nl> # Nvidia Optimus Tested-by: Lukas Wunner <lukas@wunner.de> # MacBook Pro Signed-off-by: Lukas Wunner <lukas@wunner.de> Link: https://patchwork.freedesktop.org/patch/msgid/51bd38360ff502a8c42b1ebf4405ee1d3f27118d.1520068884.git.lukas@wunner.de
647 lines
22 KiB
C
647 lines
22 KiB
C
/**
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* \file radeon_drv.c
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* ATI Radeon driver
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*
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* \author Gareth Hughes <gareth@valinux.com>
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*/
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/*
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* Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <drm/drmP.h>
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#include <drm/radeon_drm.h>
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#include "radeon_drv.h"
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#include <drm/drm_pciids.h>
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#include <linux/console.h>
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#include <linux/module.h>
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#include <linux/pm_runtime.h>
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#include <linux/vga_switcheroo.h>
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#include <linux/compat.h>
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#include <drm/drm_gem.h>
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#include <drm/drm_fb_helper.h>
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#include <drm/drm_crtc_helper.h>
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/*
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* KMS wrapper.
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* - 2.0.0 - initial interface
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* - 2.1.0 - add square tiling interface
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* - 2.2.0 - add r6xx/r7xx const buffer support
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* - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs
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* - 2.4.0 - add crtc id query
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* - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen
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* - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500)
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* 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs
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* 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query
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* 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query
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* 2.10.0 - fusion 2D tiling
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* 2.11.0 - backend map, initial compute support for the CS checker
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* 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS
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* 2.13.0 - virtual memory support, streamout
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* 2.14.0 - add evergreen tiling informations
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* 2.15.0 - add max_pipes query
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* 2.16.0 - fix evergreen 2D tiled surface calculation
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* 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx
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* 2.18.0 - r600-eg: allow "invalid" DB formats
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* 2.19.0 - r600-eg: MSAA textures
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* 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query
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* 2.21.0 - r600-r700: FMASK and CMASK
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* 2.22.0 - r600 only: RESOLVE_BOX allowed
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* 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880
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* 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures
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* 2.25.0 - eg+: new info request for num SE and num SH
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* 2.26.0 - r600-eg: fix htile size computation
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* 2.27.0 - r600-SI: Add CS ioctl support for async DMA
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* 2.28.0 - r600-eg: Add MEM_WRITE packet support
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* 2.29.0 - R500 FP16 color clear registers
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* 2.30.0 - fix for FMASK texturing
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* 2.31.0 - Add fastfb support for rs690
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* 2.32.0 - new info request for rings working
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* 2.33.0 - Add SI tiling mode array query
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* 2.34.0 - Add CIK tiling mode array query
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* 2.35.0 - Add CIK macrotile mode array query
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* 2.36.0 - Fix CIK DCE tiling setup
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* 2.37.0 - allow GS ring setup on r6xx/r7xx
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* 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN),
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* CIK: 1D and linear tiling modes contain valid PIPE_CONFIG
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* 2.39.0 - Add INFO query for number of active CUs
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* 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting
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* CS to GPU on >= r600
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* 2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support
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* 2.42.0 - Add VCE/VUI (Video Usability Information) support
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* 2.43.0 - RADEON_INFO_GPU_RESET_COUNTER
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* 2.44.0 - SET_APPEND_CNT packet3 support
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* 2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI
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* 2.46.0 - Add PFP_SYNC_ME support on evergreen
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* 2.47.0 - Add UVD_NO_OP register support
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* 2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI
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* 2.49.0 - DRM_RADEON_GEM_INFO ioctl returns correct vram_size/visible values
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* 2.50.0 - Allows unaligned shader loads on CIK. (needed by OpenGL)
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*/
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#define KMS_DRIVER_MAJOR 2
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#define KMS_DRIVER_MINOR 50
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#define KMS_DRIVER_PATCHLEVEL 0
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int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
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void radeon_driver_unload_kms(struct drm_device *dev);
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void radeon_driver_lastclose_kms(struct drm_device *dev);
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int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
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void radeon_driver_postclose_kms(struct drm_device *dev,
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struct drm_file *file_priv);
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int radeon_suspend_kms(struct drm_device *dev, bool suspend,
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bool fbcon, bool freeze);
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int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
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u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
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int radeon_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
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void radeon_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
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void radeon_driver_irq_preinstall_kms(struct drm_device *dev);
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int radeon_driver_irq_postinstall_kms(struct drm_device *dev);
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void radeon_driver_irq_uninstall_kms(struct drm_device *dev);
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irqreturn_t radeon_driver_irq_handler_kms(int irq, void *arg);
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void radeon_gem_object_free(struct drm_gem_object *obj);
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int radeon_gem_object_open(struct drm_gem_object *obj,
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struct drm_file *file_priv);
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void radeon_gem_object_close(struct drm_gem_object *obj,
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struct drm_file *file_priv);
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struct dma_buf *radeon_gem_prime_export(struct drm_device *dev,
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struct drm_gem_object *gobj,
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int flags);
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extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int crtc,
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unsigned int flags, int *vpos, int *hpos,
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ktime_t *stime, ktime_t *etime,
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const struct drm_display_mode *mode);
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extern bool radeon_is_px(struct drm_device *dev);
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extern const struct drm_ioctl_desc radeon_ioctls_kms[];
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extern int radeon_max_kms_ioctl;
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int radeon_mmap(struct file *filp, struct vm_area_struct *vma);
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int radeon_mode_dumb_mmap(struct drm_file *filp,
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struct drm_device *dev,
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uint32_t handle, uint64_t *offset_p);
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int radeon_mode_dumb_create(struct drm_file *file_priv,
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struct drm_device *dev,
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struct drm_mode_create_dumb *args);
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struct sg_table *radeon_gem_prime_get_sg_table(struct drm_gem_object *obj);
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struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev,
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struct dma_buf_attachment *,
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struct sg_table *sg);
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int radeon_gem_prime_pin(struct drm_gem_object *obj);
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void radeon_gem_prime_unpin(struct drm_gem_object *obj);
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struct reservation_object *radeon_gem_prime_res_obj(struct drm_gem_object *);
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void *radeon_gem_prime_vmap(struct drm_gem_object *obj);
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void radeon_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
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/* atpx handler */
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#if defined(CONFIG_VGA_SWITCHEROO)
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void radeon_register_atpx_handler(void);
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void radeon_unregister_atpx_handler(void);
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bool radeon_has_atpx_dgpu_power_cntl(void);
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bool radeon_is_atpx_hybrid(void);
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#else
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static inline void radeon_register_atpx_handler(void) {}
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static inline void radeon_unregister_atpx_handler(void) {}
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static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; }
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static inline bool radeon_is_atpx_hybrid(void) { return false; }
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#endif
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int radeon_no_wb;
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int radeon_modeset = -1;
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int radeon_dynclks = -1;
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int radeon_r4xx_atom = 0;
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int radeon_agpmode = 0;
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int radeon_vram_limit = 0;
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int radeon_gart_size = -1; /* auto */
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int radeon_benchmarking = 0;
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int radeon_testing = 0;
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int radeon_connector_table = 0;
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int radeon_tv = 1;
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int radeon_audio = -1;
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int radeon_disp_priority = 0;
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int radeon_hw_i2c = 0;
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int radeon_pcie_gen2 = -1;
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int radeon_msi = -1;
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int radeon_lockup_timeout = 10000;
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int radeon_fastfb = 0;
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int radeon_dpm = -1;
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int radeon_aspm = -1;
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int radeon_runtime_pm = -1;
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int radeon_hard_reset = 0;
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int radeon_vm_size = 8;
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int radeon_vm_block_size = -1;
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int radeon_deep_color = 0;
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int radeon_use_pflipirq = 2;
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int radeon_bapm = -1;
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int radeon_backlight = -1;
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int radeon_auxch = -1;
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int radeon_mst = 0;
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int radeon_uvd = 1;
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int radeon_vce = 1;
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MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
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module_param_named(no_wb, radeon_no_wb, int, 0444);
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MODULE_PARM_DESC(modeset, "Disable/Enable modesetting");
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module_param_named(modeset, radeon_modeset, int, 0400);
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MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks");
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module_param_named(dynclks, radeon_dynclks, int, 0444);
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MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx");
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module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444);
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MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
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module_param_named(vramlimit, radeon_vram_limit, int, 0600);
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MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)");
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module_param_named(agpmode, radeon_agpmode, int, 0444);
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MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
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module_param_named(gartsize, radeon_gart_size, int, 0600);
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MODULE_PARM_DESC(benchmark, "Run benchmark");
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module_param_named(benchmark, radeon_benchmarking, int, 0444);
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MODULE_PARM_DESC(test, "Run tests");
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module_param_named(test, radeon_testing, int, 0444);
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MODULE_PARM_DESC(connector_table, "Force connector table");
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module_param_named(connector_table, radeon_connector_table, int, 0444);
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MODULE_PARM_DESC(tv, "TV enable (0 = disable)");
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module_param_named(tv, radeon_tv, int, 0444);
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MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
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module_param_named(audio, radeon_audio, int, 0444);
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MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
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module_param_named(disp_priority, radeon_disp_priority, int, 0444);
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MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
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module_param_named(hw_i2c, radeon_hw_i2c, int, 0444);
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MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
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module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444);
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MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
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module_param_named(msi, radeon_msi, int, 0444);
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MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 10000 = 10 seconds, 0 = disable)");
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module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444);
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MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)");
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module_param_named(fastfb, radeon_fastfb, int, 0444);
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MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
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module_param_named(dpm, radeon_dpm, int, 0444);
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MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
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module_param_named(aspm, radeon_aspm, int, 0444);
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MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
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module_param_named(runpm, radeon_runtime_pm, int, 0444);
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MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))");
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module_param_named(hard_reset, radeon_hard_reset, int, 0444);
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MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)");
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module_param_named(vm_size, radeon_vm_size, int, 0444);
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MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
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module_param_named(vm_block_size, radeon_vm_block_size, int, 0444);
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MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
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module_param_named(deep_color, radeon_deep_color, int, 0444);
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MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))");
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module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444);
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MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
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module_param_named(bapm, radeon_bapm, int, 0444);
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MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)");
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module_param_named(backlight, radeon_backlight, int, 0444);
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MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable, -1 = auto)");
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module_param_named(auxch, radeon_auxch, int, 0444);
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MODULE_PARM_DESC(mst, "DisplayPort MST experimental support (1 = enable, 0 = disable)");
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module_param_named(mst, radeon_mst, int, 0444);
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MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)");
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module_param_named(uvd, radeon_uvd, int, 0444);
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MODULE_PARM_DESC(vce, "vce enable/disable vce support (1 = enable, 0 = disable)");
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module_param_named(vce, radeon_vce, int, 0444);
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int radeon_si_support = 1;
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MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
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module_param_named(si_support, radeon_si_support, int, 0444);
|
|
|
|
int radeon_cik_support = 1;
|
|
MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
|
|
module_param_named(cik_support, radeon_cik_support, int, 0444);
|
|
|
|
static struct pci_device_id pciidlist[] = {
|
|
radeon_PCI_IDS
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(pci, pciidlist);
|
|
|
|
static struct drm_driver kms_driver;
|
|
|
|
bool radeon_device_is_virtual(void);
|
|
|
|
static int radeon_kick_out_firmware_fb(struct pci_dev *pdev)
|
|
{
|
|
struct apertures_struct *ap;
|
|
bool primary = false;
|
|
|
|
ap = alloc_apertures(1);
|
|
if (!ap)
|
|
return -ENOMEM;
|
|
|
|
ap->ranges[0].base = pci_resource_start(pdev, 0);
|
|
ap->ranges[0].size = pci_resource_len(pdev, 0);
|
|
|
|
#ifdef CONFIG_X86
|
|
primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
|
|
#endif
|
|
drm_fb_helper_remove_conflicting_framebuffers(ap, "radeondrmfb", primary);
|
|
kfree(ap);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int radeon_pci_probe(struct pci_dev *pdev,
|
|
const struct pci_device_id *ent)
|
|
{
|
|
int ret;
|
|
|
|
if (vga_switcheroo_client_probe_defer(pdev))
|
|
return -EPROBE_DEFER;
|
|
|
|
/* Get rid of things like offb */
|
|
ret = radeon_kick_out_firmware_fb(pdev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return drm_get_pci_dev(pdev, ent, &kms_driver);
|
|
}
|
|
|
|
static void
|
|
radeon_pci_remove(struct pci_dev *pdev)
|
|
{
|
|
struct drm_device *dev = pci_get_drvdata(pdev);
|
|
|
|
drm_put_dev(dev);
|
|
}
|
|
|
|
static void
|
|
radeon_pci_shutdown(struct pci_dev *pdev)
|
|
{
|
|
/* if we are running in a VM, make sure the device
|
|
* torn down properly on reboot/shutdown
|
|
*/
|
|
if (radeon_device_is_virtual())
|
|
radeon_pci_remove(pdev);
|
|
}
|
|
|
|
static int radeon_pmops_suspend(struct device *dev)
|
|
{
|
|
struct pci_dev *pdev = to_pci_dev(dev);
|
|
struct drm_device *drm_dev = pci_get_drvdata(pdev);
|
|
return radeon_suspend_kms(drm_dev, true, true, false);
|
|
}
|
|
|
|
static int radeon_pmops_resume(struct device *dev)
|
|
{
|
|
struct pci_dev *pdev = to_pci_dev(dev);
|
|
struct drm_device *drm_dev = pci_get_drvdata(pdev);
|
|
|
|
/* GPU comes up enabled by the bios on resume */
|
|
if (radeon_is_px(drm_dev)) {
|
|
pm_runtime_disable(dev);
|
|
pm_runtime_set_active(dev);
|
|
pm_runtime_enable(dev);
|
|
}
|
|
|
|
return radeon_resume_kms(drm_dev, true, true);
|
|
}
|
|
|
|
static int radeon_pmops_freeze(struct device *dev)
|
|
{
|
|
struct pci_dev *pdev = to_pci_dev(dev);
|
|
struct drm_device *drm_dev = pci_get_drvdata(pdev);
|
|
return radeon_suspend_kms(drm_dev, false, true, true);
|
|
}
|
|
|
|
static int radeon_pmops_thaw(struct device *dev)
|
|
{
|
|
struct pci_dev *pdev = to_pci_dev(dev);
|
|
struct drm_device *drm_dev = pci_get_drvdata(pdev);
|
|
return radeon_resume_kms(drm_dev, false, true);
|
|
}
|
|
|
|
static int radeon_pmops_runtime_suspend(struct device *dev)
|
|
{
|
|
struct pci_dev *pdev = to_pci_dev(dev);
|
|
struct drm_device *drm_dev = pci_get_drvdata(pdev);
|
|
int ret;
|
|
|
|
if (!radeon_is_px(drm_dev)) {
|
|
pm_runtime_forbid(dev);
|
|
return -EBUSY;
|
|
}
|
|
|
|
drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
|
|
drm_kms_helper_poll_disable(drm_dev);
|
|
|
|
ret = radeon_suspend_kms(drm_dev, false, false, false);
|
|
pci_save_state(pdev);
|
|
pci_disable_device(pdev);
|
|
pci_ignore_hotplug(pdev);
|
|
if (radeon_is_atpx_hybrid())
|
|
pci_set_power_state(pdev, PCI_D3cold);
|
|
else if (!radeon_has_atpx_dgpu_power_cntl())
|
|
pci_set_power_state(pdev, PCI_D3hot);
|
|
drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int radeon_pmops_runtime_resume(struct device *dev)
|
|
{
|
|
struct pci_dev *pdev = to_pci_dev(dev);
|
|
struct drm_device *drm_dev = pci_get_drvdata(pdev);
|
|
int ret;
|
|
|
|
if (!radeon_is_px(drm_dev))
|
|
return -EINVAL;
|
|
|
|
drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
|
|
|
|
if (radeon_is_atpx_hybrid() ||
|
|
!radeon_has_atpx_dgpu_power_cntl())
|
|
pci_set_power_state(pdev, PCI_D0);
|
|
pci_restore_state(pdev);
|
|
ret = pci_enable_device(pdev);
|
|
if (ret)
|
|
return ret;
|
|
pci_set_master(pdev);
|
|
|
|
ret = radeon_resume_kms(drm_dev, false, false);
|
|
drm_kms_helper_poll_enable(drm_dev);
|
|
drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
|
|
return 0;
|
|
}
|
|
|
|
static int radeon_pmops_runtime_idle(struct device *dev)
|
|
{
|
|
struct pci_dev *pdev = to_pci_dev(dev);
|
|
struct drm_device *drm_dev = pci_get_drvdata(pdev);
|
|
struct drm_crtc *crtc;
|
|
|
|
if (!radeon_is_px(drm_dev)) {
|
|
pm_runtime_forbid(dev);
|
|
return -EBUSY;
|
|
}
|
|
|
|
list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
|
|
if (crtc->enabled) {
|
|
DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
|
|
return -EBUSY;
|
|
}
|
|
}
|
|
|
|
pm_runtime_mark_last_busy(dev);
|
|
pm_runtime_autosuspend(dev);
|
|
/* we don't want the main rpm_idle to call suspend - we want to autosuspend */
|
|
return 1;
|
|
}
|
|
|
|
long radeon_drm_ioctl(struct file *filp,
|
|
unsigned int cmd, unsigned long arg)
|
|
{
|
|
struct drm_file *file_priv = filp->private_data;
|
|
struct drm_device *dev;
|
|
long ret;
|
|
dev = file_priv->minor->dev;
|
|
ret = pm_runtime_get_sync(dev->dev);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
ret = drm_ioctl(filp, cmd, arg);
|
|
|
|
pm_runtime_mark_last_busy(dev->dev);
|
|
pm_runtime_put_autosuspend(dev->dev);
|
|
return ret;
|
|
}
|
|
|
|
#ifdef CONFIG_COMPAT
|
|
static long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
|
|
{
|
|
unsigned int nr = DRM_IOCTL_NR(cmd);
|
|
int ret;
|
|
|
|
if (nr < DRM_COMMAND_BASE)
|
|
return drm_compat_ioctl(filp, cmd, arg);
|
|
|
|
ret = radeon_drm_ioctl(filp, cmd, arg);
|
|
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
static const struct dev_pm_ops radeon_pm_ops = {
|
|
.suspend = radeon_pmops_suspend,
|
|
.resume = radeon_pmops_resume,
|
|
.freeze = radeon_pmops_freeze,
|
|
.thaw = radeon_pmops_thaw,
|
|
.poweroff = radeon_pmops_freeze,
|
|
.restore = radeon_pmops_resume,
|
|
.runtime_suspend = radeon_pmops_runtime_suspend,
|
|
.runtime_resume = radeon_pmops_runtime_resume,
|
|
.runtime_idle = radeon_pmops_runtime_idle,
|
|
};
|
|
|
|
static const struct file_operations radeon_driver_kms_fops = {
|
|
.owner = THIS_MODULE,
|
|
.open = drm_open,
|
|
.release = drm_release,
|
|
.unlocked_ioctl = radeon_drm_ioctl,
|
|
.mmap = radeon_mmap,
|
|
.poll = drm_poll,
|
|
.read = drm_read,
|
|
#ifdef CONFIG_COMPAT
|
|
.compat_ioctl = radeon_kms_compat_ioctl,
|
|
#endif
|
|
};
|
|
|
|
static bool
|
|
radeon_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe,
|
|
bool in_vblank_irq, int *vpos, int *hpos,
|
|
ktime_t *stime, ktime_t *etime,
|
|
const struct drm_display_mode *mode)
|
|
{
|
|
return radeon_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,
|
|
stime, etime, mode);
|
|
}
|
|
|
|
static struct drm_driver kms_driver = {
|
|
.driver_features =
|
|
DRIVER_USE_AGP |
|
|
DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
|
|
DRIVER_PRIME | DRIVER_RENDER,
|
|
.load = radeon_driver_load_kms,
|
|
.open = radeon_driver_open_kms,
|
|
.postclose = radeon_driver_postclose_kms,
|
|
.lastclose = radeon_driver_lastclose_kms,
|
|
.unload = radeon_driver_unload_kms,
|
|
.get_vblank_counter = radeon_get_vblank_counter_kms,
|
|
.enable_vblank = radeon_enable_vblank_kms,
|
|
.disable_vblank = radeon_disable_vblank_kms,
|
|
.get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos,
|
|
.get_scanout_position = radeon_get_crtc_scanout_position,
|
|
.irq_preinstall = radeon_driver_irq_preinstall_kms,
|
|
.irq_postinstall = radeon_driver_irq_postinstall_kms,
|
|
.irq_uninstall = radeon_driver_irq_uninstall_kms,
|
|
.irq_handler = radeon_driver_irq_handler_kms,
|
|
.ioctls = radeon_ioctls_kms,
|
|
.gem_free_object_unlocked = radeon_gem_object_free,
|
|
.gem_open_object = radeon_gem_object_open,
|
|
.gem_close_object = radeon_gem_object_close,
|
|
.dumb_create = radeon_mode_dumb_create,
|
|
.dumb_map_offset = radeon_mode_dumb_mmap,
|
|
.fops = &radeon_driver_kms_fops,
|
|
|
|
.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
|
|
.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
|
|
.gem_prime_export = radeon_gem_prime_export,
|
|
.gem_prime_import = drm_gem_prime_import,
|
|
.gem_prime_pin = radeon_gem_prime_pin,
|
|
.gem_prime_unpin = radeon_gem_prime_unpin,
|
|
.gem_prime_res_obj = radeon_gem_prime_res_obj,
|
|
.gem_prime_get_sg_table = radeon_gem_prime_get_sg_table,
|
|
.gem_prime_import_sg_table = radeon_gem_prime_import_sg_table,
|
|
.gem_prime_vmap = radeon_gem_prime_vmap,
|
|
.gem_prime_vunmap = radeon_gem_prime_vunmap,
|
|
|
|
.name = DRIVER_NAME,
|
|
.desc = DRIVER_DESC,
|
|
.date = DRIVER_DATE,
|
|
.major = KMS_DRIVER_MAJOR,
|
|
.minor = KMS_DRIVER_MINOR,
|
|
.patchlevel = KMS_DRIVER_PATCHLEVEL,
|
|
};
|
|
|
|
static struct drm_driver *driver;
|
|
static struct pci_driver *pdriver;
|
|
|
|
static struct pci_driver radeon_kms_pci_driver = {
|
|
.name = DRIVER_NAME,
|
|
.id_table = pciidlist,
|
|
.probe = radeon_pci_probe,
|
|
.remove = radeon_pci_remove,
|
|
.shutdown = radeon_pci_shutdown,
|
|
.driver.pm = &radeon_pm_ops,
|
|
};
|
|
|
|
static int __init radeon_init(void)
|
|
{
|
|
if (vgacon_text_force() && radeon_modeset == -1) {
|
|
DRM_INFO("VGACON disable radeon kernel modesetting.\n");
|
|
radeon_modeset = 0;
|
|
}
|
|
/* set to modesetting by default if not nomodeset */
|
|
if (radeon_modeset == -1)
|
|
radeon_modeset = 1;
|
|
|
|
if (radeon_modeset == 1) {
|
|
DRM_INFO("radeon kernel modesetting enabled.\n");
|
|
driver = &kms_driver;
|
|
pdriver = &radeon_kms_pci_driver;
|
|
driver->driver_features |= DRIVER_MODESET;
|
|
driver->num_ioctls = radeon_max_kms_ioctl;
|
|
radeon_register_atpx_handler();
|
|
|
|
} else {
|
|
DRM_ERROR("No UMS support in radeon module!\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
return pci_register_driver(pdriver);
|
|
}
|
|
|
|
static void __exit radeon_exit(void)
|
|
{
|
|
pci_unregister_driver(pdriver);
|
|
radeon_unregister_atpx_handler();
|
|
}
|
|
|
|
module_init(radeon_init);
|
|
module_exit(radeon_exit);
|
|
|
|
MODULE_AUTHOR(DRIVER_AUTHOR);
|
|
MODULE_DESCRIPTION(DRIVER_DESC);
|
|
MODULE_LICENSE("GPL and additional rights");
|