![Jérôme Glisse](/assets/img/avatar_default.png)
When GPU fails to resume we can not trust that value we write to GPU memory will post and we might get garbage (more like 0xffffffff on x86) when reading them back. This trigger out of range memory access in the kernel inside the vce resume code path. This patch use canonical value to compute offset instead of reading back value from GPU memory. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Jérôme Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
385 lines
8.9 KiB
C
385 lines
8.9 KiB
C
/*
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* Copyright 2013 Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* Authors: Christian König <christian.koenig@amd.com>
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*/
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#include <linux/firmware.h>
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#include <drm/drmP.h>
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#include "radeon.h"
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#include "radeon_asic.h"
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#include "sid.h"
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#define VCE_V1_0_FW_SIZE (256 * 1024)
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#define VCE_V1_0_STACK_SIZE (64 * 1024)
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#define VCE_V1_0_DATA_SIZE (7808 * (RADEON_MAX_VCE_HANDLES + 1))
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struct vce_v1_0_fw_signature
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{
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int32_t off;
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uint32_t len;
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int32_t num;
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struct {
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uint32_t chip_id;
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uint32_t keyselect;
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uint32_t nonce[4];
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uint32_t sigval[4];
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} val[8];
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};
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/**
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* vce_v1_0_get_rptr - get read pointer
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*
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* @rdev: radeon_device pointer
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* @ring: radeon_ring pointer
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*
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* Returns the current hardware read pointer
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*/
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uint32_t vce_v1_0_get_rptr(struct radeon_device *rdev,
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struct radeon_ring *ring)
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{
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if (ring->idx == TN_RING_TYPE_VCE1_INDEX)
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return RREG32(VCE_RB_RPTR);
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else
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return RREG32(VCE_RB_RPTR2);
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}
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/**
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* vce_v1_0_get_wptr - get write pointer
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*
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* @rdev: radeon_device pointer
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* @ring: radeon_ring pointer
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*
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* Returns the current hardware write pointer
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*/
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uint32_t vce_v1_0_get_wptr(struct radeon_device *rdev,
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struct radeon_ring *ring)
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{
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if (ring->idx == TN_RING_TYPE_VCE1_INDEX)
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return RREG32(VCE_RB_WPTR);
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else
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return RREG32(VCE_RB_WPTR2);
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}
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/**
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* vce_v1_0_set_wptr - set write pointer
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*
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* @rdev: radeon_device pointer
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* @ring: radeon_ring pointer
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*
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* Commits the write pointer to the hardware
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*/
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void vce_v1_0_set_wptr(struct radeon_device *rdev,
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struct radeon_ring *ring)
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{
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if (ring->idx == TN_RING_TYPE_VCE1_INDEX)
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WREG32(VCE_RB_WPTR, ring->wptr);
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else
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WREG32(VCE_RB_WPTR2, ring->wptr);
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}
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void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable)
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{
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u32 tmp;
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if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_VCE_MGCG)) {
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tmp = RREG32(VCE_CLOCK_GATING_A);
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tmp |= CGC_DYN_CLOCK_MODE;
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WREG32(VCE_CLOCK_GATING_A, tmp);
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tmp = RREG32(VCE_UENC_CLOCK_GATING);
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tmp &= ~0x1ff000;
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tmp |= 0xff800000;
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WREG32(VCE_UENC_CLOCK_GATING, tmp);
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tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
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tmp &= ~0x3ff;
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WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
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} else {
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tmp = RREG32(VCE_CLOCK_GATING_A);
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tmp &= ~CGC_DYN_CLOCK_MODE;
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WREG32(VCE_CLOCK_GATING_A, tmp);
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tmp = RREG32(VCE_UENC_CLOCK_GATING);
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tmp |= 0x1ff000;
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tmp &= ~0xff800000;
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WREG32(VCE_UENC_CLOCK_GATING, tmp);
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tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
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tmp |= 0x3ff;
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WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
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}
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}
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static void vce_v1_0_init_cg(struct radeon_device *rdev)
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{
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u32 tmp;
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tmp = RREG32(VCE_CLOCK_GATING_A);
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tmp |= CGC_DYN_CLOCK_MODE;
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WREG32(VCE_CLOCK_GATING_A, tmp);
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tmp = RREG32(VCE_CLOCK_GATING_B);
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tmp |= 0x1e;
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tmp &= ~0xe100e1;
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WREG32(VCE_CLOCK_GATING_B, tmp);
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tmp = RREG32(VCE_UENC_CLOCK_GATING);
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tmp &= ~0xff9ff000;
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WREG32(VCE_UENC_CLOCK_GATING, tmp);
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tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
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tmp &= ~0x3ff;
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WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
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}
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int vce_v1_0_load_fw(struct radeon_device *rdev, uint32_t *data)
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{
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struct vce_v1_0_fw_signature *sign = (void*)rdev->vce_fw->data;
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uint32_t chip_id;
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int i;
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switch (rdev->family) {
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case CHIP_TAHITI:
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chip_id = 0x01000014;
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break;
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case CHIP_VERDE:
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chip_id = 0x01000015;
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break;
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case CHIP_PITCAIRN:
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case CHIP_OLAND:
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chip_id = 0x01000016;
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break;
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case CHIP_ARUBA:
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chip_id = 0x01000017;
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break;
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default:
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return -EINVAL;
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}
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for (i = 0; i < le32_to_cpu(sign->num); ++i) {
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if (le32_to_cpu(sign->val[i].chip_id) == chip_id)
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break;
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}
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if (i == le32_to_cpu(sign->num))
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return -EINVAL;
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data += (256 - 64) / 4;
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data[0] = sign->val[i].nonce[0];
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data[1] = sign->val[i].nonce[1];
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data[2] = sign->val[i].nonce[2];
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data[3] = sign->val[i].nonce[3];
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data[4] = cpu_to_le32(le32_to_cpu(sign->len) + 64);
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memset(&data[5], 0, 44);
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memcpy(&data[16], &sign[1], rdev->vce_fw->size - sizeof(*sign));
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data += (le32_to_cpu(sign->len) + 64) / 4;
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data[0] = sign->val[i].sigval[0];
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data[1] = sign->val[i].sigval[1];
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data[2] = sign->val[i].sigval[2];
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data[3] = sign->val[i].sigval[3];
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rdev->vce.keyselect = le32_to_cpu(sign->val[i].keyselect);
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return 0;
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}
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unsigned vce_v1_0_bo_size(struct radeon_device *rdev)
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{
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WARN_ON(VCE_V1_0_FW_SIZE < rdev->vce_fw->size);
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return VCE_V1_0_FW_SIZE + VCE_V1_0_STACK_SIZE + VCE_V1_0_DATA_SIZE;
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}
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int vce_v1_0_resume(struct radeon_device *rdev)
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{
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uint64_t addr = rdev->vce.gpu_addr;
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uint32_t size;
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int i;
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WREG32_P(VCE_CLOCK_GATING_A, 0, ~(1 << 16));
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WREG32_P(VCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);
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WREG32_P(VCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
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WREG32(VCE_CLOCK_GATING_B, 0);
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WREG32_P(VCE_LMI_FW_PERIODIC_CTRL, 0x4, ~0x4);
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WREG32(VCE_LMI_CTRL, 0x00398000);
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WREG32_P(VCE_LMI_CACHE_CTRL, 0x0, ~0x1);
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WREG32(VCE_LMI_SWAP_CNTL, 0);
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WREG32(VCE_LMI_SWAP_CNTL1, 0);
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WREG32(VCE_LMI_VM_CTRL, 0);
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WREG32(VCE_VCPU_SCRATCH7, RADEON_MAX_VCE_HANDLES);
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addr += 256;
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size = VCE_V1_0_FW_SIZE;
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WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);
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WREG32(VCE_VCPU_CACHE_SIZE0, size);
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addr += size;
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size = VCE_V1_0_STACK_SIZE;
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WREG32(VCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff);
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WREG32(VCE_VCPU_CACHE_SIZE1, size);
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addr += size;
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size = VCE_V1_0_DATA_SIZE;
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WREG32(VCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff);
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WREG32(VCE_VCPU_CACHE_SIZE2, size);
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WREG32_P(VCE_LMI_CTRL2, 0x0, ~0x100);
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WREG32(VCE_LMI_FW_START_KEYSEL, rdev->vce.keyselect);
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for (i = 0; i < 10; ++i) {
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mdelay(10);
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if (RREG32(VCE_FW_REG_STATUS) & VCE_FW_REG_STATUS_DONE)
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break;
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}
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if (i == 10)
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return -ETIMEDOUT;
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if (!(RREG32(VCE_FW_REG_STATUS) & VCE_FW_REG_STATUS_PASS))
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return -EINVAL;
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for (i = 0; i < 10; ++i) {
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mdelay(10);
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if (!(RREG32(VCE_FW_REG_STATUS) & VCE_FW_REG_STATUS_BUSY))
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break;
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}
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if (i == 10)
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return -ETIMEDOUT;
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vce_v1_0_init_cg(rdev);
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return 0;
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}
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/**
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* vce_v1_0_start - start VCE block
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*
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* @rdev: radeon_device pointer
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*
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* Setup and start the VCE block
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*/
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int vce_v1_0_start(struct radeon_device *rdev)
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{
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struct radeon_ring *ring;
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int i, j, r;
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/* set BUSY flag */
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WREG32_P(VCE_STATUS, 1, ~1);
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ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX];
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WREG32(VCE_RB_RPTR, ring->wptr);
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WREG32(VCE_RB_WPTR, ring->wptr);
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WREG32(VCE_RB_BASE_LO, ring->gpu_addr);
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WREG32(VCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
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WREG32(VCE_RB_SIZE, ring->ring_size / 4);
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ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX];
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WREG32(VCE_RB_RPTR2, ring->wptr);
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WREG32(VCE_RB_WPTR2, ring->wptr);
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WREG32(VCE_RB_BASE_LO2, ring->gpu_addr);
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WREG32(VCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
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WREG32(VCE_RB_SIZE2, ring->ring_size / 4);
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WREG32_P(VCE_VCPU_CNTL, VCE_CLK_EN, ~VCE_CLK_EN);
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WREG32_P(VCE_SOFT_RESET,
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VCE_ECPU_SOFT_RESET |
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VCE_FME_SOFT_RESET, ~(
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VCE_ECPU_SOFT_RESET |
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VCE_FME_SOFT_RESET));
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mdelay(100);
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WREG32_P(VCE_SOFT_RESET, 0, ~(
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VCE_ECPU_SOFT_RESET |
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VCE_FME_SOFT_RESET));
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for (i = 0; i < 10; ++i) {
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uint32_t status;
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for (j = 0; j < 100; ++j) {
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status = RREG32(VCE_STATUS);
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if (status & 2)
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break;
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mdelay(10);
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}
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r = 0;
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if (status & 2)
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break;
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DRM_ERROR("VCE not responding, trying to reset the ECPU!!!\n");
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WREG32_P(VCE_SOFT_RESET, VCE_ECPU_SOFT_RESET, ~VCE_ECPU_SOFT_RESET);
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mdelay(10);
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WREG32_P(VCE_SOFT_RESET, 0, ~VCE_ECPU_SOFT_RESET);
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mdelay(10);
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r = -1;
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}
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/* clear BUSY flag */
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WREG32_P(VCE_STATUS, 0, ~1);
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if (r) {
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DRM_ERROR("VCE not responding, giving up!!!\n");
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return r;
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}
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return 0;
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}
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int vce_v1_0_init(struct radeon_device *rdev)
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{
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struct radeon_ring *ring;
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int r;
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r = vce_v1_0_start(rdev);
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if (r)
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return r;
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ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX];
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ring->ready = true;
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r = radeon_ring_test(rdev, TN_RING_TYPE_VCE1_INDEX, ring);
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if (r) {
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ring->ready = false;
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return r;
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}
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ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX];
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ring->ready = true;
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r = radeon_ring_test(rdev, TN_RING_TYPE_VCE2_INDEX, ring);
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if (r) {
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ring->ready = false;
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return r;
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}
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DRM_INFO("VCE initialized successfully.\n");
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return 0;
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}
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