31f5232eff
While debugging inverted color from the HDMI output on the A10, I found that the lowest 3 bits were set. These were cleared on A20 boards that had normal display output. By manually toggling these bits the mapping of the color components to these bits was found. While these are not used anywhere, it would be nice to document them somewhere. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171014040252.9621-7-wens@csie.org
302 lines
10 KiB
C
302 lines
10 KiB
C
/*
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* Copyright (C) 2016 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#ifndef _SUN4I_HDMI_H_
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#define _SUN4I_HDMI_H_
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#include <drm/drm_connector.h>
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#include <drm/drm_encoder.h>
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#include <linux/regmap.h>
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#include <media/cec-pin.h>
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#define SUN4I_HDMI_CTRL_REG 0x004
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#define SUN4I_HDMI_CTRL_ENABLE BIT(31)
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#define SUN4I_HDMI_IRQ_REG 0x008
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#define SUN4I_HDMI_IRQ_STA_MASK 0x73
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#define SUN4I_HDMI_IRQ_STA_FIFO_OF BIT(1)
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#define SUN4I_HDMI_IRQ_STA_FIFO_UF BIT(0)
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#define SUN4I_HDMI_HPD_REG 0x00c
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#define SUN4I_HDMI_HPD_HIGH BIT(0)
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#define SUN4I_HDMI_VID_CTRL_REG 0x010
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#define SUN4I_HDMI_VID_CTRL_ENABLE BIT(31)
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#define SUN4I_HDMI_VID_CTRL_HDMI_MODE BIT(30)
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#define SUN4I_HDMI_VID_TIMING_ACT_REG 0x014
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#define SUN4I_HDMI_VID_TIMING_BP_REG 0x018
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#define SUN4I_HDMI_VID_TIMING_FP_REG 0x01c
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#define SUN4I_HDMI_VID_TIMING_SPW_REG 0x020
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#define SUN4I_HDMI_VID_TIMING_X(x) ((((x) - 1) & GENMASK(11, 0)))
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#define SUN4I_HDMI_VID_TIMING_Y(y) ((((y) - 1) & GENMASK(11, 0)) << 16)
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#define SUN4I_HDMI_VID_TIMING_POL_REG 0x024
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#define SUN4I_HDMI_VID_TIMING_POL_TX_CLK (0x3e0 << 16)
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#define SUN4I_HDMI_VID_TIMING_POL_VSYNC BIT(1)
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#define SUN4I_HDMI_VID_TIMING_POL_HSYNC BIT(0)
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#define SUN4I_HDMI_AVI_INFOFRAME_REG(n) (0x080 + (n))
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#define SUN4I_HDMI_PAD_CTRL0_REG 0x200
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#define SUN4I_HDMI_PAD_CTRL0_BIASEN BIT(31)
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#define SUN4I_HDMI_PAD_CTRL0_LDOCEN BIT(30)
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#define SUN4I_HDMI_PAD_CTRL0_LDODEN BIT(29)
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#define SUN4I_HDMI_PAD_CTRL0_PWENC BIT(28)
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#define SUN4I_HDMI_PAD_CTRL0_PWEND BIT(27)
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#define SUN4I_HDMI_PAD_CTRL0_PWENG BIT(26)
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#define SUN4I_HDMI_PAD_CTRL0_CKEN BIT(25)
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#define SUN4I_HDMI_PAD_CTRL0_TXEN BIT(23)
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#define SUN4I_HDMI_PAD_CTRL1_REG 0x204
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#define SUN4I_HDMI_PAD_CTRL1_UNKNOWN BIT(24) /* set on A31 */
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#define SUN4I_HDMI_PAD_CTRL1_AMP_OPT BIT(23)
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#define SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT BIT(22)
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#define SUN4I_HDMI_PAD_CTRL1_EMP_OPT BIT(20)
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#define SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT BIT(19)
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#define SUN4I_HDMI_PAD_CTRL1_PWSCK BIT(18)
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#define SUN4I_HDMI_PAD_CTRL1_PWSDT BIT(17)
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#define SUN4I_HDMI_PAD_CTRL1_REG_DEN BIT(15)
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#define SUN4I_HDMI_PAD_CTRL1_REG_DENCK BIT(14)
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#define SUN4I_HDMI_PAD_CTRL1_REG_EMP(n) (((n) & 7) << 10)
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#define SUN4I_HDMI_PAD_CTRL1_HALVE_CLK BIT(6)
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#define SUN4I_HDMI_PAD_CTRL1_REG_AMP(n) (((n) & 7) << 3)
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/* These bits seem to invert the TMDS data channels */
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#define SUN4I_HDMI_PAD_CTRL1_INVERT_R BIT(2)
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#define SUN4I_HDMI_PAD_CTRL1_INVERT_G BIT(1)
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#define SUN4I_HDMI_PAD_CTRL1_INVERT_B BIT(0)
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#define SUN4I_HDMI_PLL_CTRL_REG 0x208
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#define SUN4I_HDMI_PLL_CTRL_PLL_EN BIT(31)
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#define SUN4I_HDMI_PLL_CTRL_BWS BIT(30)
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#define SUN4I_HDMI_PLL_CTRL_HV_IS_33 BIT(29)
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#define SUN4I_HDMI_PLL_CTRL_LDO1_EN BIT(28)
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#define SUN4I_HDMI_PLL_CTRL_LDO2_EN BIT(27)
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#define SUN4I_HDMI_PLL_CTRL_SDIV2 BIT(25)
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#define SUN4I_HDMI_PLL_CTRL_VCO_GAIN(n) (((n) & 7) << 20)
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#define SUN4I_HDMI_PLL_CTRL_S(n) (((n) & 7) << 17)
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#define SUN4I_HDMI_PLL_CTRL_CP_S(n) (((n) & 0x1f) << 12)
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#define SUN4I_HDMI_PLL_CTRL_CS(n) (((n) & 0xf) << 8)
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#define SUN4I_HDMI_PLL_CTRL_DIV(n) (((n) & 0xf) << 4)
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#define SUN4I_HDMI_PLL_CTRL_DIV_MASK GENMASK(7, 4)
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#define SUN4I_HDMI_PLL_CTRL_VCO_S(n) ((n) & 0xf)
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#define SUN4I_HDMI_PLL_DBG0_REG 0x20c
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#define SUN4I_HDMI_PLL_DBG0_TMDS_PARENT(n) (((n) & 1) << 21)
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#define SUN4I_HDMI_PLL_DBG0_TMDS_PARENT_MASK BIT(21)
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#define SUN4I_HDMI_PLL_DBG0_TMDS_PARENT_SHIFT 21
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#define SUN4I_HDMI_CEC 0x214
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#define SUN4I_HDMI_CEC_ENABLE BIT(11)
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#define SUN4I_HDMI_CEC_TX BIT(9)
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#define SUN4I_HDMI_CEC_RX BIT(8)
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#define SUN4I_HDMI_PKT_CTRL_REG(n) (0x2f0 + (4 * (n)))
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#define SUN4I_HDMI_PKT_CTRL_TYPE(n, t) ((t) << (((n) % 4) * 4))
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#define SUN4I_HDMI_UNKNOWN_REG 0x300
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#define SUN4I_HDMI_UNKNOWN_INPUT_SYNC BIT(27)
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#define SUN4I_HDMI_DDC_CTRL_REG 0x500
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#define SUN4I_HDMI_DDC_CTRL_ENABLE BIT(31)
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#define SUN4I_HDMI_DDC_CTRL_START_CMD BIT(30)
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#define SUN4I_HDMI_DDC_CTRL_FIFO_DIR_MASK BIT(8)
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#define SUN4I_HDMI_DDC_CTRL_FIFO_DIR_WRITE (1 << 8)
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#define SUN4I_HDMI_DDC_CTRL_FIFO_DIR_READ (0 << 8)
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#define SUN4I_HDMI_DDC_CTRL_RESET BIT(0)
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#define SUN4I_HDMI_DDC_ADDR_REG 0x504
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#define SUN4I_HDMI_DDC_ADDR_SEGMENT(seg) (((seg) & 0xff) << 24)
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#define SUN4I_HDMI_DDC_ADDR_EDDC(addr) (((addr) & 0xff) << 16)
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#define SUN4I_HDMI_DDC_ADDR_OFFSET(off) (((off) & 0xff) << 8)
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#define SUN4I_HDMI_DDC_ADDR_SLAVE(addr) ((addr) & 0xff)
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#define SUN4I_HDMI_DDC_INT_STATUS_REG 0x50c
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#define SUN4I_HDMI_DDC_INT_STATUS_ILLEGAL_FIFO_OPERATION BIT(7)
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#define SUN4I_HDMI_DDC_INT_STATUS_DDC_RX_FIFO_UNDERFLOW BIT(6)
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#define SUN4I_HDMI_DDC_INT_STATUS_DDC_TX_FIFO_OVERFLOW BIT(5)
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#define SUN4I_HDMI_DDC_INT_STATUS_FIFO_REQUEST BIT(4)
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#define SUN4I_HDMI_DDC_INT_STATUS_ARBITRATION_ERROR BIT(3)
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#define SUN4I_HDMI_DDC_INT_STATUS_ACK_ERROR BIT(2)
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#define SUN4I_HDMI_DDC_INT_STATUS_BUS_ERROR BIT(1)
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#define SUN4I_HDMI_DDC_INT_STATUS_TRANSFER_COMPLETE BIT(0)
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#define SUN4I_HDMI_DDC_FIFO_CTRL_REG 0x510
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#define SUN4I_HDMI_DDC_FIFO_CTRL_CLEAR BIT(31)
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#define SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES(n) (((n) & 0xf) << 4)
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#define SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES_MASK GENMASK(7, 4)
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#define SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES_MAX (BIT(4) - 1)
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#define SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES(n) ((n) & 0xf)
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#define SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES_MASK GENMASK(3, 0)
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#define SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES_MAX (BIT(4) - 1)
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#define SUN4I_HDMI_DDC_FIFO_DATA_REG 0x518
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#define SUN4I_HDMI_DDC_BYTE_COUNT_REG 0x51c
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#define SUN4I_HDMI_DDC_BYTE_COUNT_MAX (BIT(10) - 1)
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#define SUN4I_HDMI_DDC_CMD_REG 0x520
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#define SUN4I_HDMI_DDC_CMD_EXPLICIT_EDDC_READ 6
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#define SUN4I_HDMI_DDC_CMD_IMPLICIT_READ 5
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#define SUN4I_HDMI_DDC_CMD_IMPLICIT_WRITE 3
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#define SUN4I_HDMI_DDC_CLK_REG 0x528
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#define SUN4I_HDMI_DDC_CLK_M(m) (((m) & 0x7) << 3)
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#define SUN4I_HDMI_DDC_CLK_N(n) ((n) & 0x7)
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#define SUN4I_HDMI_DDC_LINE_CTRL_REG 0x540
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#define SUN4I_HDMI_DDC_LINE_CTRL_SDA_ENABLE BIT(9)
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#define SUN4I_HDMI_DDC_LINE_CTRL_SCL_ENABLE BIT(8)
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#define SUN4I_HDMI_DDC_FIFO_SIZE 16
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/* A31 specific */
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#define SUN6I_HDMI_DDC_CTRL_REG 0x500
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#define SUN6I_HDMI_DDC_CTRL_RESET BIT(31)
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#define SUN6I_HDMI_DDC_CTRL_START_CMD BIT(27)
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#define SUN6I_HDMI_DDC_CTRL_SDA_ENABLE BIT(6)
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#define SUN6I_HDMI_DDC_CTRL_SCL_ENABLE BIT(4)
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#define SUN6I_HDMI_DDC_CTRL_ENABLE BIT(0)
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#define SUN6I_HDMI_DDC_CMD_REG 0x508
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#define SUN6I_HDMI_DDC_CMD_BYTE_COUNT(count) ((count) << 16)
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/* command types in lower 3 bits are the same as sun4i */
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#define SUN6I_HDMI_DDC_ADDR_REG 0x50c
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#define SUN6I_HDMI_DDC_ADDR_SEGMENT(seg) (((seg) & 0xff) << 24)
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#define SUN6I_HDMI_DDC_ADDR_EDDC(addr) (((addr) & 0xff) << 16)
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#define SUN6I_HDMI_DDC_ADDR_OFFSET(off) (((off) & 0xff) << 8)
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#define SUN6I_HDMI_DDC_ADDR_SLAVE(addr) (((addr) & 0xff) << 1)
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#define SUN6I_HDMI_DDC_INT_STATUS_REG 0x514
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#define SUN6I_HDMI_DDC_INT_STATUS_TIMEOUT BIT(8)
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/* lower 8 bits are the same as sun4i */
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#define SUN6I_HDMI_DDC_FIFO_CTRL_REG 0x518
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#define SUN6I_HDMI_DDC_FIFO_CTRL_CLEAR BIT(15)
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/* lower 9 bits are the same as sun4i */
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#define SUN6I_HDMI_DDC_CLK_REG 0x520
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/* DDC CLK bit fields are the same, but the formula is not */
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#define SUN6I_HDMI_DDC_FIFO_DATA_REG 0x580
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enum sun4i_hdmi_pkt_type {
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SUN4I_HDMI_PKT_AVI = 2,
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SUN4I_HDMI_PKT_END = 15,
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};
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struct sun4i_hdmi_variant {
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bool has_ddc_parent_clk;
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bool has_reset_control;
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u32 pad_ctrl0_init_val;
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u32 pad_ctrl1_init_val;
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u32 pll_ctrl_init_val;
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struct reg_field ddc_clk_reg;
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u8 ddc_clk_pre_divider;
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u8 ddc_clk_m_offset;
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u8 tmds_clk_div_offset;
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/* Register fields for I2C adapter */
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struct reg_field field_ddc_en;
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struct reg_field field_ddc_start;
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struct reg_field field_ddc_reset;
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struct reg_field field_ddc_addr_reg;
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struct reg_field field_ddc_slave_addr;
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struct reg_field field_ddc_int_mask;
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struct reg_field field_ddc_int_status;
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struct reg_field field_ddc_fifo_clear;
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struct reg_field field_ddc_fifo_rx_thres;
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struct reg_field field_ddc_fifo_tx_thres;
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struct reg_field field_ddc_byte_count;
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struct reg_field field_ddc_cmd;
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struct reg_field field_ddc_sda_en;
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struct reg_field field_ddc_sck_en;
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/* DDC FIFO register offset */
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u32 ddc_fifo_reg;
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/*
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* DDC FIFO threshold boundary conditions
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*
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* This is used to cope with the threshold boundary condition
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* being slightly different on sun5i and sun6i.
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*
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* On sun5i the threshold is exclusive, i.e. does not include,
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* the value of the threshold. ( > for RX; < for TX )
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* On sun6i the threshold is inclusive, i.e. includes, the
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* value of the threshold. ( >= for RX; <= for TX )
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*/
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bool ddc_fifo_thres_incl;
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bool ddc_fifo_has_dir;
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};
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struct sun4i_hdmi {
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struct drm_connector connector;
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struct drm_encoder encoder;
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struct device *dev;
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void __iomem *base;
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struct regmap *regmap;
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/* Reset control */
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struct reset_control *reset;
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/* Parent clocks */
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struct clk *bus_clk;
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struct clk *mod_clk;
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struct clk *ddc_parent_clk;
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struct clk *pll0_clk;
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struct clk *pll1_clk;
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/* And the clocks we create */
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struct clk *ddc_clk;
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struct clk *tmds_clk;
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struct i2c_adapter *i2c;
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/* Regmap fields for I2C adapter */
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struct regmap_field *field_ddc_en;
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struct regmap_field *field_ddc_start;
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struct regmap_field *field_ddc_reset;
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struct regmap_field *field_ddc_addr_reg;
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struct regmap_field *field_ddc_slave_addr;
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struct regmap_field *field_ddc_int_mask;
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struct regmap_field *field_ddc_int_status;
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struct regmap_field *field_ddc_fifo_clear;
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struct regmap_field *field_ddc_fifo_rx_thres;
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struct regmap_field *field_ddc_fifo_tx_thres;
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struct regmap_field *field_ddc_byte_count;
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struct regmap_field *field_ddc_cmd;
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struct regmap_field *field_ddc_sda_en;
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struct regmap_field *field_ddc_sck_en;
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struct sun4i_drv *drv;
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bool hdmi_monitor;
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struct cec_adapter *cec_adap;
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const struct sun4i_hdmi_variant *variant;
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};
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int sun4i_ddc_create(struct sun4i_hdmi *hdmi, struct clk *clk);
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int sun4i_tmds_create(struct sun4i_hdmi *hdmi);
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int sun4i_hdmi_i2c_create(struct device *dev, struct sun4i_hdmi *hdmi);
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#endif /* _SUN4I_HDMI_H_ */
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