![Jonathan Liu](/assets/img/avatar_default.png)
It was only checking the divider when determing the closest match if
it could not match the requested rate exactly.
For a projector connected to an Olimex A20-OLinuXino-LIME using HDMI
with a native resolution of 1280x800 and pixel clock of 83.5 MHz, this
resulted in 1280x800 mode not being available and the following in dmesg
when the kernel is booted with drm.debug=0x3e:
[drm:drm_mode_debug_printmodeline] Modeline 37:"1280x800" 60 83500 1280 1352 1480 1680 800 810 816 831 0x48 0x5
[drm:drm_mode_prune_invalid] Not using 1280x800 mode: NOCLOCK
Fixes: 9c5681011a
("drm/sun4i: Add HDMI support")
Signed-off-by: Jonathan Liu <net147@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180109020323.11852-4-net147@gmail.com
240 lines
5.3 KiB
C
240 lines
5.3 KiB
C
/*
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* Copyright (C) 2016 Free Electrons
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* Copyright (C) 2016 NextThing Co
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <linux/clk-provider.h>
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#include "sun4i_hdmi.h"
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struct sun4i_tmds {
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struct clk_hw hw;
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struct sun4i_hdmi *hdmi;
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u8 div_offset;
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};
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static inline struct sun4i_tmds *hw_to_tmds(struct clk_hw *hw)
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{
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return container_of(hw, struct sun4i_tmds, hw);
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}
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static unsigned long sun4i_tmds_calc_divider(unsigned long rate,
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unsigned long parent_rate,
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u8 div_offset,
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u8 *div,
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bool *half)
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{
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unsigned long best_rate = 0;
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u8 best_m = 0, m;
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bool is_double;
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for (m = div_offset ?: 1; m < (16 + div_offset); m++) {
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u8 d;
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for (d = 1; d < 3; d++) {
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unsigned long tmp_rate;
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tmp_rate = parent_rate / m / d;
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if (tmp_rate > rate)
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continue;
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if (!best_rate ||
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(rate - tmp_rate) < (rate - best_rate)) {
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best_rate = tmp_rate;
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best_m = m;
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is_double = d;
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}
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}
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}
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if (div && half) {
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*div = best_m;
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*half = is_double;
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}
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return best_rate;
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}
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static int sun4i_tmds_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct sun4i_tmds *tmds = hw_to_tmds(hw);
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struct clk_hw *parent = NULL;
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unsigned long best_parent = 0;
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unsigned long rate = req->rate;
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int best_div = 1, best_half = 1;
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int i, j, p;
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/*
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* We only consider PLL3, since the TCON is very likely to be
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* clocked from it, and to have the same rate than our HDMI
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* clock, so we should not need to do anything.
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*/
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for (p = 0; p < clk_hw_get_num_parents(hw); p++) {
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parent = clk_hw_get_parent_by_index(hw, p);
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if (!parent)
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continue;
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for (i = 1; i < 3; i++) {
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for (j = tmds->div_offset ?: 1;
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j < (16 + tmds->div_offset); j++) {
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unsigned long ideal = rate * i * j;
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unsigned long rounded;
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rounded = clk_hw_round_rate(parent, ideal);
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if (rounded == ideal) {
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best_parent = rounded;
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best_half = i;
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best_div = j;
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goto out;
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}
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if (!best_parent ||
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abs(rate - rounded / i / j) <
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abs(rate - best_parent / best_half /
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best_div)) {
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best_parent = rounded;
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best_half = i;
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best_div = j;
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}
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}
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}
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}
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if (!parent)
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return -EINVAL;
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out:
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req->rate = best_parent / best_half / best_div;
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req->best_parent_rate = best_parent;
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req->best_parent_hw = parent;
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return 0;
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}
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static unsigned long sun4i_tmds_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct sun4i_tmds *tmds = hw_to_tmds(hw);
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u32 reg;
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reg = readl(tmds->hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
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if (reg & SUN4I_HDMI_PAD_CTRL1_HALVE_CLK)
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parent_rate /= 2;
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reg = readl(tmds->hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
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reg = ((reg >> 4) & 0xf) + tmds->div_offset;
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if (!reg)
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reg = 1;
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return parent_rate / reg;
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}
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static int sun4i_tmds_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct sun4i_tmds *tmds = hw_to_tmds(hw);
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bool half;
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u32 reg;
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u8 div;
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sun4i_tmds_calc_divider(rate, parent_rate, tmds->div_offset,
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&div, &half);
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reg = readl(tmds->hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
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reg &= ~SUN4I_HDMI_PAD_CTRL1_HALVE_CLK;
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if (half)
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reg |= SUN4I_HDMI_PAD_CTRL1_HALVE_CLK;
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writel(reg, tmds->hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
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reg = readl(tmds->hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
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reg &= ~SUN4I_HDMI_PLL_CTRL_DIV_MASK;
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writel(reg | SUN4I_HDMI_PLL_CTRL_DIV(div - tmds->div_offset),
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tmds->hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
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return 0;
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}
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static u8 sun4i_tmds_get_parent(struct clk_hw *hw)
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{
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struct sun4i_tmds *tmds = hw_to_tmds(hw);
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u32 reg;
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reg = readl(tmds->hdmi->base + SUN4I_HDMI_PLL_DBG0_REG);
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return ((reg & SUN4I_HDMI_PLL_DBG0_TMDS_PARENT_MASK) >>
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SUN4I_HDMI_PLL_DBG0_TMDS_PARENT_SHIFT);
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}
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static int sun4i_tmds_set_parent(struct clk_hw *hw, u8 index)
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{
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struct sun4i_tmds *tmds = hw_to_tmds(hw);
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u32 reg;
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if (index > 1)
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return -EINVAL;
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reg = readl(tmds->hdmi->base + SUN4I_HDMI_PLL_DBG0_REG);
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reg &= ~SUN4I_HDMI_PLL_DBG0_TMDS_PARENT_MASK;
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writel(reg | SUN4I_HDMI_PLL_DBG0_TMDS_PARENT(index),
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tmds->hdmi->base + SUN4I_HDMI_PLL_DBG0_REG);
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return 0;
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}
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static const struct clk_ops sun4i_tmds_ops = {
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.determine_rate = sun4i_tmds_determine_rate,
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.recalc_rate = sun4i_tmds_recalc_rate,
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.set_rate = sun4i_tmds_set_rate,
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.get_parent = sun4i_tmds_get_parent,
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.set_parent = sun4i_tmds_set_parent,
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};
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int sun4i_tmds_create(struct sun4i_hdmi *hdmi)
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{
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struct clk_init_data init;
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struct sun4i_tmds *tmds;
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const char *parents[2];
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parents[0] = __clk_get_name(hdmi->pll0_clk);
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if (!parents[0])
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return -ENODEV;
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parents[1] = __clk_get_name(hdmi->pll1_clk);
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if (!parents[1])
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return -ENODEV;
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tmds = devm_kzalloc(hdmi->dev, sizeof(*tmds), GFP_KERNEL);
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if (!tmds)
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return -ENOMEM;
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init.name = "hdmi-tmds";
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init.ops = &sun4i_tmds_ops;
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init.parent_names = parents;
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init.num_parents = 2;
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init.flags = CLK_SET_RATE_PARENT;
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tmds->hdmi = hdmi;
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tmds->hw.init = &init;
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tmds->div_offset = hdmi->variant->tmds_clk_div_offset;
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hdmi->tmds_clk = devm_clk_register(hdmi->dev, &tmds->hw);
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if (IS_ERR(hdmi->tmds_clk))
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return PTR_ERR(hdmi->tmds_clk);
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return 0;
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}
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