![Maxime Ripard](/assets/img/avatar_default.png)
It seems like the mixer can only run properly when clocked at 150MHz. In order to have something more robust than simply a fire-and-forget assigned-clocks-rate, let's put that in the code. Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Link: https://patchwork.freedesktop.org/patch/msgid/f5f05307972ed05250e8094b302d68b9e7e167f6.1513854122.git-series.maxime.ripard@free-electrons.com
154 lines
4.8 KiB
C
154 lines
4.8 KiB
C
/*
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* Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#ifndef _SUN8I_MIXER_H_
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#define _SUN8I_MIXER_H_
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#include <linux/clk.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include "sun8i_csc.h"
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#include "sunxi_engine.h"
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#define SUN8I_MIXER_SIZE(w, h) (((h) - 1) << 16 | ((w) - 1))
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#define SUN8I_MIXER_COORD(x, y) ((y) << 16 | (x))
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#define SUN8I_MIXER_GLOBAL_CTL 0x0
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#define SUN8I_MIXER_GLOBAL_STATUS 0x4
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#define SUN8I_MIXER_GLOBAL_DBUFF 0x8
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#define SUN8I_MIXER_GLOBAL_SIZE 0xc
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#define SUN8I_MIXER_GLOBAL_CTL_RT_EN BIT(0)
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#define SUN8I_MIXER_GLOBAL_DBUFF_ENABLE BIT(0)
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#define SUN8I_MIXER_BLEND_PIPE_CTL 0x1000
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#define SUN8I_MIXER_BLEND_ATTR_FCOLOR(x) (0x1004 + 0x10 * (x) + 0x0)
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#define SUN8I_MIXER_BLEND_ATTR_INSIZE(x) (0x1004 + 0x10 * (x) + 0x4)
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#define SUN8I_MIXER_BLEND_ATTR_COORD(x) (0x1004 + 0x10 * (x) + 0x8)
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#define SUN8I_MIXER_BLEND_ROUTE 0x1080
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#define SUN8I_MIXER_BLEND_PREMULTIPLY 0x1084
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#define SUN8I_MIXER_BLEND_BKCOLOR 0x1088
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#define SUN8I_MIXER_BLEND_OUTSIZE 0x108c
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#define SUN8I_MIXER_BLEND_MODE(x) (0x1090 + 0x04 * (x))
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#define SUN8I_MIXER_BLEND_CK_CTL 0x10b0
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#define SUN8I_MIXER_BLEND_CK_CFG 0x10b4
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#define SUN8I_MIXER_BLEND_CK_MAX(x) (0x10c0 + 0x04 * (x))
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#define SUN8I_MIXER_BLEND_CK_MIN(x) (0x10e0 + 0x04 * (x))
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#define SUN8I_MIXER_BLEND_OUTCTL 0x10fc
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#define SUN8I_MIXER_BLEND_PIPE_CTL_EN(pipe) BIT(8 + pipe)
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#define SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(pipe) BIT(pipe)
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/* colors are always in AARRGGBB format */
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#define SUN8I_MIXER_BLEND_COLOR_BLACK 0xff000000
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/* The following numbers are some still unknown magic numbers */
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#define SUN8I_MIXER_BLEND_MODE_DEF 0x03010301
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#define SUN8I_MIXER_BLEND_OUTCTL_INTERLACED BIT(1)
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#define SUN8I_MIXER_FBFMT_ARGB8888 0
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#define SUN8I_MIXER_FBFMT_ABGR8888 1
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#define SUN8I_MIXER_FBFMT_RGBA8888 2
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#define SUN8I_MIXER_FBFMT_BGRA8888 3
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#define SUN8I_MIXER_FBFMT_XRGB8888 4
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#define SUN8I_MIXER_FBFMT_XBGR8888 5
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#define SUN8I_MIXER_FBFMT_RGBX8888 6
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#define SUN8I_MIXER_FBFMT_BGRX8888 7
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#define SUN8I_MIXER_FBFMT_RGB888 8
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#define SUN8I_MIXER_FBFMT_BGR888 9
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#define SUN8I_MIXER_FBFMT_RGB565 10
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#define SUN8I_MIXER_FBFMT_BGR565 11
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#define SUN8I_MIXER_FBFMT_ARGB4444 12
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#define SUN8I_MIXER_FBFMT_ABGR4444 13
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#define SUN8I_MIXER_FBFMT_RGBA4444 14
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#define SUN8I_MIXER_FBFMT_BGRA4444 15
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#define SUN8I_MIXER_FBFMT_ARGB1555 16
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#define SUN8I_MIXER_FBFMT_ABGR1555 17
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#define SUN8I_MIXER_FBFMT_RGBA5551 18
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#define SUN8I_MIXER_FBFMT_BGRA5551 19
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#define SUN8I_MIXER_FBFMT_YUYV 0
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#define SUN8I_MIXER_FBFMT_UYVY 1
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#define SUN8I_MIXER_FBFMT_YVYU 2
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#define SUN8I_MIXER_FBFMT_VYUY 3
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#define SUN8I_MIXER_FBFMT_NV16 4
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#define SUN8I_MIXER_FBFMT_NV61 5
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#define SUN8I_MIXER_FBFMT_YUV422 6
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/* format 7 doesn't exist */
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#define SUN8I_MIXER_FBFMT_NV12 8
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#define SUN8I_MIXER_FBFMT_NV21 9
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#define SUN8I_MIXER_FBFMT_YUV420 10
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/* format 11 doesn't exist */
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/* format 12 is semi-planar YUV411 UVUV */
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/* format 13 is semi-planar YUV411 VUVU */
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#define SUN8I_MIXER_FBFMT_YUV411 14
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/*
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* These sub-engines are still unknown now, the EN registers are here only to
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* be used to disable these sub-engines.
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*/
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#define SUN8I_MIXER_FCE_EN 0xa0000
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#define SUN8I_MIXER_BWS_EN 0xa2000
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#define SUN8I_MIXER_LTI_EN 0xa4000
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#define SUN8I_MIXER_PEAK_EN 0xa6000
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#define SUN8I_MIXER_ASE_EN 0xa8000
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#define SUN8I_MIXER_FCC_EN 0xaa000
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#define SUN8I_MIXER_DCSC_EN 0xb0000
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struct de2_fmt_info {
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u32 drm_fmt;
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u32 de2_fmt;
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bool rgb;
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enum sun8i_csc_mode csc;
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};
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/**
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* struct sun8i_mixer_cfg - mixer HW configuration
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* @vi_num: number of VI channels
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* @ui_num: number of UI channels
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* @scaler_mask: bitmask which tells which channel supports scaling
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* First, scaler supports for VI channels is defined and after that, scaler
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* support for UI channels. For example, if mixer has 2 VI channels without
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* scaler and 2 UI channels with scaler, bitmask would be 0xC.
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* @ccsc: select set of CCSC base addresses
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* Set value to 0 if this is first mixer or second mixer with VEP support.
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* Set value to 1 if this is second mixer without VEP support. Other values
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* are invalid.
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* @mod_rate: module clock rate that needs to be set in order to have
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* a functional block.
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*/
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struct sun8i_mixer_cfg {
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int vi_num;
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int ui_num;
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int scaler_mask;
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int ccsc;
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unsigned long mod_rate;
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};
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struct sun8i_mixer {
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struct sunxi_engine engine;
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const struct sun8i_mixer_cfg *cfg;
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struct reset_control *reset;
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struct clk *bus_clk;
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struct clk *mod_clk;
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};
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static inline struct sun8i_mixer *
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engine_to_sun8i_mixer(struct sunxi_engine *engine)
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{
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return container_of(engine, struct sun8i_mixer, engine);
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}
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const struct de2_fmt_info *sun8i_mixer_format_info(u32 format);
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#endif /* _SUN8I_MIXER_H_ */
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