![Ville Syrjälä](/assets/img/avatar_default.png)
Move the plane clip rectangle handling into drm_atomic_helper_check_plane_state(). Drivers no longer have to worry about such mundane details. v2: Convert armada, rcar, and sun4i as well v3: Resolve simple_kms_helper conflict Cc: Liviu Dudau <liviu.dudau@arm.com> Cc: Brian Starkey <brian.starkey@arm.com> Cc: Mali DP Maintainers <malidp@foss.arm.com> Cc: Daniel Vetter <daniel.vetter@intel.com> Cc: Gustavo Padovan <gustavo@padovan.org> Cc: Sean Paul <seanpaul@chromium.org> Cc: Philipp Zabel <p.zabel@pengutronix.de> Cc: CK Hu <ck.hu@mediatek.com> Cc: Neil Armstrong <narmstrong@baylibre.com> Cc: Rob Clark <robdclark@gmail.com> Cc: Ben Skeggs <bskeggs@redhat.com> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: Sandy Huang <hjc@rock-chips.com> Cc: "Heiko Stübner" <heiko@sntech.de> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: VMware Graphics <linux-graphics-maintainer@vmware.com> Cc: Sinclair Yeh <syeh@vmware.com> Cc: Thomas Hellstrom <thellstrom@vmware.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Archit Taneja <architt@codeaurora.org> Cc: linux-amlogic@lists.infradead.org Cc: linux-arm-msm@vger.kernel.org Cc: freedreno@lists.freedesktop.org Cc: nouveau@lists.freedesktop.org Cc: linux-renesas-soc@vger.kernel.org Cc: linux-tegra@vger.kernel.org Cc: Russell King <rmk+kernel@armlinux.org.uk> Suggested-by: Daniel Vetter <daniel@ffwll.ch> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Archit Taneja <architt@codeaurora.org> #msm Link: https://patchwork.freedesktop.org/patch/msgid/20180123170857.13818-5-ville.syrjala@linux.intel.com Acked-by: Liviu Dudau <liviu.dudau@arm.com> #hdlcd,malidp Acked-by: Philipp Zabel <p.zabel@pengutronix.de> #imx,mtk Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Sinclair Yeh <syeh@vmware.com> #vmwgfx Acked-by: Neil Armstrong <narmstrong@baylibre.com> #meson Acked-by: Shawn Guo <shawnguo@kernel.org> #zte
385 lines
10 KiB
C
385 lines
10 KiB
C
/*
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* Copyright (C) Jernej Skrabec <jernej.skrabec@siol.net>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <drm/drm_atomic.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_fb_cma_helper.h>
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#include <drm/drm_gem_cma_helper.h>
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#include <drm/drm_plane_helper.h>
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#include <drm/drmP.h>
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#include "sun8i_vi_layer.h"
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#include "sun8i_mixer.h"
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#include "sun8i_vi_scaler.h"
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static void sun8i_vi_layer_enable(struct sun8i_mixer *mixer, int channel,
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int overlay, bool enable)
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{
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u32 val;
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DRM_DEBUG_DRIVER("%sabling VI channel %d overlay %d\n",
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enable ? "En" : "Dis", channel, overlay);
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if (enable)
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val = SUN8I_MIXER_CHAN_VI_LAYER_ATTR_EN;
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else
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val = 0;
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regmap_update_bits(mixer->engine.regs,
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SUN8I_MIXER_CHAN_VI_LAYER_ATTR(channel, overlay),
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SUN8I_MIXER_CHAN_VI_LAYER_ATTR_EN, val);
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if (enable)
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val = SUN8I_MIXER_BLEND_PIPE_CTL_EN(channel);
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else
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val = 0;
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regmap_update_bits(mixer->engine.regs,
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SUN8I_MIXER_BLEND_PIPE_CTL,
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SUN8I_MIXER_BLEND_PIPE_CTL_EN(channel), val);
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}
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static int sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel,
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int overlay, struct drm_plane *plane)
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{
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struct drm_plane_state *state = plane->state;
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const struct drm_format_info *format = state->fb->format;
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u32 src_w, src_h, dst_w, dst_h;
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u32 outsize, insize;
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u32 hphase, vphase;
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bool subsampled;
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DRM_DEBUG_DRIVER("Updating VI channel %d overlay %d\n",
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channel, overlay);
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src_w = drm_rect_width(&state->src) >> 16;
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src_h = drm_rect_height(&state->src) >> 16;
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dst_w = drm_rect_width(&state->dst);
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dst_h = drm_rect_height(&state->dst);
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hphase = state->src.x1 & 0xffff;
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vphase = state->src.y1 & 0xffff;
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/* make coordinates dividable by subsampling factor */
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if (format->hsub > 1) {
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int mask, remainder;
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mask = format->hsub - 1;
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remainder = (state->src.x1 >> 16) & mask;
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src_w = (src_w + remainder) & ~mask;
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hphase += remainder << 16;
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}
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if (format->vsub > 1) {
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int mask, remainder;
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mask = format->vsub - 1;
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remainder = (state->src.y1 >> 16) & mask;
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src_h = (src_h + remainder) & ~mask;
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vphase += remainder << 16;
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}
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insize = SUN8I_MIXER_SIZE(src_w, src_h);
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outsize = SUN8I_MIXER_SIZE(dst_w, dst_h);
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/* Set height and width */
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DRM_DEBUG_DRIVER("Layer source offset X: %d Y: %d\n",
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(state->src.x1 >> 16) & ~(format->hsub - 1),
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(state->src.y1 >> 16) & ~(format->vsub - 1));
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DRM_DEBUG_DRIVER("Layer source size W: %d H: %d\n", src_w, src_h);
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regmap_write(mixer->engine.regs,
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SUN8I_MIXER_CHAN_VI_LAYER_SIZE(channel, overlay),
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insize);
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regmap_write(mixer->engine.regs,
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SUN8I_MIXER_CHAN_VI_OVL_SIZE(channel),
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insize);
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/*
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* Scaler must be enabled for subsampled formats, so it scales
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* chroma to same size as luma.
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*/
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subsampled = format->hsub > 1 || format->vsub > 1;
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if (insize != outsize || subsampled || hphase || vphase) {
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u32 hscale, vscale;
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DRM_DEBUG_DRIVER("HW scaling is enabled\n");
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hscale = state->src_w / state->crtc_w;
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vscale = state->src_h / state->crtc_h;
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sun8i_vi_scaler_setup(mixer, channel, src_w, src_h, dst_w,
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dst_h, hscale, vscale, hphase, vphase,
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format);
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sun8i_vi_scaler_enable(mixer, channel, true);
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} else {
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DRM_DEBUG_DRIVER("HW scaling is not needed\n");
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sun8i_vi_scaler_enable(mixer, channel, false);
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}
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/* Set base coordinates */
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DRM_DEBUG_DRIVER("Layer destination coordinates X: %d Y: %d\n",
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state->dst.x1, state->dst.y1);
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DRM_DEBUG_DRIVER("Layer destination size W: %d H: %d\n", dst_w, dst_h);
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regmap_write(mixer->engine.regs,
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SUN8I_MIXER_BLEND_ATTR_COORD(channel),
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SUN8I_MIXER_COORD(state->dst.x1, state->dst.y1));
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regmap_write(mixer->engine.regs,
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SUN8I_MIXER_BLEND_ATTR_INSIZE(channel),
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outsize);
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return 0;
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}
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static int sun8i_vi_layer_update_formats(struct sun8i_mixer *mixer, int channel,
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int overlay, struct drm_plane *plane)
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{
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struct drm_plane_state *state = plane->state;
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const struct de2_fmt_info *fmt_info;
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u32 val;
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fmt_info = sun8i_mixer_format_info(state->fb->format->format);
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if (!fmt_info) {
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DRM_DEBUG_DRIVER("Invalid format\n");
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return -EINVAL;
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}
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val = fmt_info->de2_fmt << SUN8I_MIXER_CHAN_VI_LAYER_ATTR_FBFMT_OFFSET;
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regmap_update_bits(mixer->engine.regs,
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SUN8I_MIXER_CHAN_VI_LAYER_ATTR(channel, overlay),
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SUN8I_MIXER_CHAN_VI_LAYER_ATTR_FBFMT_MASK, val);
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if (fmt_info->csc != SUN8I_CSC_MODE_OFF) {
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sun8i_csc_set_ccsc_coefficients(mixer, channel, fmt_info->csc);
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sun8i_csc_enable_ccsc(mixer, channel, true);
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} else {
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sun8i_csc_enable_ccsc(mixer, channel, false);
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}
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if (fmt_info->rgb)
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val = SUN8I_MIXER_CHAN_VI_LAYER_ATTR_RGB_MODE;
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else
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val = 0;
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regmap_update_bits(mixer->engine.regs,
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SUN8I_MIXER_CHAN_VI_LAYER_ATTR(channel, overlay),
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SUN8I_MIXER_CHAN_VI_LAYER_ATTR_RGB_MODE, val);
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return 0;
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}
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static int sun8i_vi_layer_update_buffer(struct sun8i_mixer *mixer, int channel,
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int overlay, struct drm_plane *plane)
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{
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struct drm_plane_state *state = plane->state;
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struct drm_framebuffer *fb = state->fb;
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const struct drm_format_info *format = fb->format;
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struct drm_gem_cma_object *gem;
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u32 dx, dy, src_x, src_y;
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dma_addr_t paddr;
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int i;
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/* Adjust x and y to be dividable by subsampling factor */
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src_x = (state->src.x1 >> 16) & ~(format->hsub - 1);
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src_y = (state->src.y1 >> 16) & ~(format->vsub - 1);
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for (i = 0; i < format->num_planes; i++) {
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/* Get the physical address of the buffer in memory */
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gem = drm_fb_cma_get_gem_obj(fb, i);
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DRM_DEBUG_DRIVER("Using GEM @ %pad\n", &gem->paddr);
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/* Compute the start of the displayed memory */
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paddr = gem->paddr + fb->offsets[i];
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dx = src_x;
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dy = src_y;
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if (i > 0) {
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dx /= format->hsub;
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dy /= format->vsub;
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}
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/* Fixup framebuffer address for src coordinates */
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paddr += dx * format->cpp[i];
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paddr += dy * fb->pitches[i];
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/* Set the line width */
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DRM_DEBUG_DRIVER("Layer %d. line width: %d bytes\n",
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i + 1, fb->pitches[i]);
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regmap_write(mixer->engine.regs,
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SUN8I_MIXER_CHAN_VI_LAYER_PITCH(channel,
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overlay, i),
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fb->pitches[i]);
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DRM_DEBUG_DRIVER("Setting %d. buffer address to %pad\n",
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i + 1, &paddr);
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regmap_write(mixer->engine.regs,
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SUN8I_MIXER_CHAN_VI_LAYER_TOP_LADDR(channel,
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overlay, i),
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lower_32_bits(paddr));
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}
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return 0;
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}
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static int sun8i_vi_layer_atomic_check(struct drm_plane *plane,
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struct drm_plane_state *state)
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{
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struct sun8i_vi_layer *layer = plane_to_sun8i_vi_layer(plane);
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struct drm_crtc *crtc = state->crtc;
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struct drm_crtc_state *crtc_state;
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int min_scale, max_scale;
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if (!crtc)
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return 0;
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crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
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if (WARN_ON(!crtc_state))
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return -EINVAL;
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min_scale = DRM_PLANE_HELPER_NO_SCALING;
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max_scale = DRM_PLANE_HELPER_NO_SCALING;
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if (layer->mixer->cfg->scaler_mask & BIT(layer->channel)) {
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min_scale = SUN8I_VI_SCALER_SCALE_MIN;
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max_scale = SUN8I_VI_SCALER_SCALE_MAX;
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}
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return drm_atomic_helper_check_plane_state(state, crtc_state,
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min_scale, max_scale,
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true, true);
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}
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static void sun8i_vi_layer_atomic_disable(struct drm_plane *plane,
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struct drm_plane_state *old_state)
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{
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struct sun8i_vi_layer *layer = plane_to_sun8i_vi_layer(plane);
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struct sun8i_mixer *mixer = layer->mixer;
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sun8i_vi_layer_enable(mixer, layer->channel, layer->overlay, false);
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}
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static void sun8i_vi_layer_atomic_update(struct drm_plane *plane,
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struct drm_plane_state *old_state)
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{
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struct sun8i_vi_layer *layer = plane_to_sun8i_vi_layer(plane);
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struct sun8i_mixer *mixer = layer->mixer;
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if (!plane->state->visible) {
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sun8i_vi_layer_enable(mixer, layer->channel,
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layer->overlay, false);
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return;
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}
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sun8i_vi_layer_update_coord(mixer, layer->channel,
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layer->overlay, plane);
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sun8i_vi_layer_update_formats(mixer, layer->channel,
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layer->overlay, plane);
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sun8i_vi_layer_update_buffer(mixer, layer->channel,
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layer->overlay, plane);
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sun8i_vi_layer_enable(mixer, layer->channel, layer->overlay, true);
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}
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static struct drm_plane_helper_funcs sun8i_vi_layer_helper_funcs = {
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.atomic_check = sun8i_vi_layer_atomic_check,
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.atomic_disable = sun8i_vi_layer_atomic_disable,
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.atomic_update = sun8i_vi_layer_atomic_update,
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};
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static const struct drm_plane_funcs sun8i_vi_layer_funcs = {
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.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
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.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
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.destroy = drm_plane_cleanup,
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.disable_plane = drm_atomic_helper_disable_plane,
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.reset = drm_atomic_helper_plane_reset,
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.update_plane = drm_atomic_helper_update_plane,
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};
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/*
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* While all RGB formats are supported, VI planes don't support
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* alpha blending, so there is no point having formats with alpha
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* channel if their opaque analog exist.
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*/
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static const u32 sun8i_vi_layer_formats[] = {
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DRM_FORMAT_ABGR1555,
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DRM_FORMAT_ABGR4444,
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DRM_FORMAT_ARGB1555,
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DRM_FORMAT_ARGB4444,
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DRM_FORMAT_BGR565,
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DRM_FORMAT_BGR888,
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DRM_FORMAT_BGRA5551,
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DRM_FORMAT_BGRA4444,
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DRM_FORMAT_BGRX8888,
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DRM_FORMAT_RGB565,
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DRM_FORMAT_RGB888,
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DRM_FORMAT_RGBA4444,
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DRM_FORMAT_RGBA5551,
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DRM_FORMAT_RGBX8888,
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DRM_FORMAT_XBGR8888,
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DRM_FORMAT_XRGB8888,
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DRM_FORMAT_NV16,
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DRM_FORMAT_NV12,
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DRM_FORMAT_NV21,
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DRM_FORMAT_NV61,
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DRM_FORMAT_UYVY,
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DRM_FORMAT_VYUY,
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DRM_FORMAT_YUYV,
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DRM_FORMAT_YVYU,
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DRM_FORMAT_YUV411,
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DRM_FORMAT_YUV420,
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DRM_FORMAT_YUV422,
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DRM_FORMAT_YUV444,
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DRM_FORMAT_YVU411,
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DRM_FORMAT_YVU420,
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DRM_FORMAT_YVU422,
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DRM_FORMAT_YVU444,
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};
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struct sun8i_vi_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
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struct sun8i_mixer *mixer,
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int index)
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{
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struct sun8i_vi_layer *layer;
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int ret;
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layer = devm_kzalloc(drm->dev, sizeof(*layer), GFP_KERNEL);
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if (!layer)
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return ERR_PTR(-ENOMEM);
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/* possible crtcs are set later */
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ret = drm_universal_plane_init(drm, &layer->plane, 0,
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&sun8i_vi_layer_funcs,
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sun8i_vi_layer_formats,
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ARRAY_SIZE(sun8i_vi_layer_formats),
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NULL, DRM_PLANE_TYPE_OVERLAY, NULL);
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if (ret) {
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dev_err(drm->dev, "Couldn't initialize layer\n");
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return ERR_PTR(ret);
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}
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/* fixed zpos for now */
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ret = drm_plane_create_zpos_immutable_property(&layer->plane, index);
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if (ret) {
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dev_err(drm->dev, "Couldn't add zpos property\n");
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return ERR_PTR(ret);
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}
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drm_plane_helper_add(&layer->plane, &sun8i_vi_layer_helper_funcs);
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layer->mixer = mixer;
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layer->channel = index;
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layer->overlay = 0;
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return layer;
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}
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