c4755fb906
The display architecture has changed in several significant ways with the new Tegra186 SoC. Shared between all display controllers is a set of common resources referred to as the display hub. The hub generates accesses to memory and feeds them into various composition pipelines, each of which being a window that can be assigned to arbitrary heads. Atomic state is subclassed in order to track the global bandwidth requirements and select and adjust the hub clocks appropriately. The plane code is shared to a large degree with earlier SoC generations, except where the programming differs. Signed-off-by: Thierry Reding <treding@nvidia.com>
26 lines
329 B
Makefile
26 lines
329 B
Makefile
# SPDX-License-Identifier: GPL-2.0
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ccflags-$(CONFIG_DRM_TEGRA_DEBUG) += -DDEBUG
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tegra-drm-y := \
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drm.o \
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gem.o \
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fb.o \
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hub.o \
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plane.o \
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dc.o \
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output.o \
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rgb.o \
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hdmi.o \
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mipi-phy.o \
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dsi.o \
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sor.o \
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dpaux.o \
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gr2d.o \
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gr3d.o \
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falcon.o \
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vic.o
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tegra-drm-y += trace.o
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obj-$(CONFIG_DRM_TEGRA) += tegra-drm.o
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