![Boris Brezillon](/assets/img/avatar_default.png)
The V3D engine has various hardware counters which might be interesting to userspace performance analysis tools. Expose new ioctls to create/destroy a performance monitor object and query the counter values of this perfmance monitor. Note that a perfomance monitor is given an ID that is only valid on the file descriptor it has been allocated from. A performance monitor can be attached to a CL submission and the driver will enable HW counters for this request and update the performance monitor values at the end of the job. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Eric Anholt <eric@anholt.net> Link: https://patchwork.freedesktop.org/patch/msgid/20180112090926.12538-1-boris.brezillon@free-electrons.com
291 lines
8.2 KiB
C
291 lines
8.2 KiB
C
/*
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* Copyright © 2014 Broadcom
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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/**
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* DOC: Interrupt management for the V3D engine
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*
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* We have an interrupt status register (V3D_INTCTL) which reports
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* interrupts, and where writing 1 bits clears those interrupts.
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* There are also a pair of interrupt registers
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* (V3D_INTENA/V3D_INTDIS) where writing a 1 to their bits enables or
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* disables that specific interrupt, and 0s written are ignored
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* (reading either one returns the set of enabled interrupts).
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*
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* When we take a binning flush done interrupt, we need to submit the
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* next frame for binning and move the finished frame to the render
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* thread.
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*
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* When we take a render frame interrupt, we need to wake the
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* processes waiting for some frame to be done, and get the next frame
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* submitted ASAP (so the hardware doesn't sit idle when there's work
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* to do).
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*
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* When we take the binner out of memory interrupt, we need to
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* allocate some new memory and pass it to the binner so that the
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* current job can make progress.
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*/
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#include "vc4_drv.h"
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#include "vc4_regs.h"
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#define V3D_DRIVER_IRQS (V3D_INT_OUTOMEM | \
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V3D_INT_FLDONE | \
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V3D_INT_FRDONE)
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DECLARE_WAIT_QUEUE_HEAD(render_wait);
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static void
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vc4_overflow_mem_work(struct work_struct *work)
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{
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struct vc4_dev *vc4 =
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container_of(work, struct vc4_dev, overflow_mem_work);
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struct vc4_bo *bo = vc4->bin_bo;
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int bin_bo_slot;
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struct vc4_exec_info *exec;
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unsigned long irqflags;
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bin_bo_slot = vc4_v3d_get_bin_slot(vc4);
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if (bin_bo_slot < 0) {
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DRM_ERROR("Couldn't allocate binner overflow mem\n");
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return;
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}
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spin_lock_irqsave(&vc4->job_lock, irqflags);
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if (vc4->bin_alloc_overflow) {
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/* If we had overflow memory allocated previously,
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* then that chunk will free when the current bin job
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* is done. If we don't have a bin job running, then
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* the chunk will be done whenever the list of render
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* jobs has drained.
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*/
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exec = vc4_first_bin_job(vc4);
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if (!exec)
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exec = vc4_last_render_job(vc4);
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if (exec) {
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exec->bin_slots |= vc4->bin_alloc_overflow;
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} else {
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/* There's nothing queued in the hardware, so
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* the old slot is free immediately.
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*/
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vc4->bin_alloc_used &= ~vc4->bin_alloc_overflow;
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}
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}
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vc4->bin_alloc_overflow = BIT(bin_bo_slot);
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V3D_WRITE(V3D_BPOA, bo->base.paddr + bin_bo_slot * vc4->bin_alloc_size);
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V3D_WRITE(V3D_BPOS, bo->base.base.size);
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V3D_WRITE(V3D_INTCTL, V3D_INT_OUTOMEM);
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V3D_WRITE(V3D_INTENA, V3D_INT_OUTOMEM);
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spin_unlock_irqrestore(&vc4->job_lock, irqflags);
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}
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static void
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vc4_irq_finish_bin_job(struct drm_device *dev)
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{
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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struct vc4_exec_info *next, *exec = vc4_first_bin_job(vc4);
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if (!exec)
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return;
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vc4_move_job_to_render(dev, exec);
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next = vc4_first_bin_job(vc4);
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/* Only submit the next job in the bin list if it matches the perfmon
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* attached to the one that just finished (or if both jobs don't have
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* perfmon attached to them).
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*/
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if (next && next->perfmon == exec->perfmon)
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vc4_submit_next_bin_job(dev);
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}
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static void
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vc4_cancel_bin_job(struct drm_device *dev)
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{
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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struct vc4_exec_info *exec = vc4_first_bin_job(vc4);
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if (!exec)
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return;
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/* Stop the perfmon so that the next bin job can be started. */
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if (exec->perfmon)
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vc4_perfmon_stop(vc4, exec->perfmon, false);
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list_move_tail(&exec->head, &vc4->bin_job_list);
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vc4_submit_next_bin_job(dev);
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}
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static void
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vc4_irq_finish_render_job(struct drm_device *dev)
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{
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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struct vc4_exec_info *exec = vc4_first_render_job(vc4);
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struct vc4_exec_info *nextbin, *nextrender;
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if (!exec)
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return;
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vc4->finished_seqno++;
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list_move_tail(&exec->head, &vc4->job_done_list);
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nextbin = vc4_first_bin_job(vc4);
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nextrender = vc4_first_render_job(vc4);
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/* Only stop the perfmon if following jobs in the queue don't expect it
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* to be enabled.
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*/
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if (exec->perfmon && !nextrender &&
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(!nextbin || nextbin->perfmon != exec->perfmon))
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vc4_perfmon_stop(vc4, exec->perfmon, true);
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/* If there's a render job waiting, start it. If this is not the case
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* we may have to unblock the binner if it's been stalled because of
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* perfmon (this can be checked by comparing the perfmon attached to
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* the finished renderjob to the one attached to the next bin job: if
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* they don't match, this means the binner is stalled and should be
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* restarted).
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*/
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if (nextrender)
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vc4_submit_next_render_job(dev);
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else if (nextbin && nextbin->perfmon != exec->perfmon)
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vc4_submit_next_bin_job(dev);
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if (exec->fence) {
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dma_fence_signal_locked(exec->fence);
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dma_fence_put(exec->fence);
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exec->fence = NULL;
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}
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wake_up_all(&vc4->job_wait_queue);
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schedule_work(&vc4->job_done_work);
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}
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irqreturn_t
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vc4_irq(int irq, void *arg)
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{
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struct drm_device *dev = arg;
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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uint32_t intctl;
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irqreturn_t status = IRQ_NONE;
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barrier();
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intctl = V3D_READ(V3D_INTCTL);
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/* Acknowledge the interrupts we're handling here. The binner
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* last flush / render frame done interrupt will be cleared,
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* while OUTOMEM will stay high until the underlying cause is
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* cleared.
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*/
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V3D_WRITE(V3D_INTCTL, intctl);
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if (intctl & V3D_INT_OUTOMEM) {
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/* Disable OUTOMEM until the work is done. */
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V3D_WRITE(V3D_INTDIS, V3D_INT_OUTOMEM);
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schedule_work(&vc4->overflow_mem_work);
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status = IRQ_HANDLED;
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}
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if (intctl & V3D_INT_FLDONE) {
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spin_lock(&vc4->job_lock);
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vc4_irq_finish_bin_job(dev);
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spin_unlock(&vc4->job_lock);
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status = IRQ_HANDLED;
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}
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if (intctl & V3D_INT_FRDONE) {
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spin_lock(&vc4->job_lock);
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vc4_irq_finish_render_job(dev);
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spin_unlock(&vc4->job_lock);
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status = IRQ_HANDLED;
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}
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return status;
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}
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void
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vc4_irq_preinstall(struct drm_device *dev)
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{
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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init_waitqueue_head(&vc4->job_wait_queue);
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INIT_WORK(&vc4->overflow_mem_work, vc4_overflow_mem_work);
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/* Clear any pending interrupts someone might have left around
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* for us.
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*/
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V3D_WRITE(V3D_INTCTL, V3D_DRIVER_IRQS);
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}
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int
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vc4_irq_postinstall(struct drm_device *dev)
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{
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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/* Enable both the render done and out of memory interrupts. */
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V3D_WRITE(V3D_INTENA, V3D_DRIVER_IRQS);
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return 0;
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}
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void
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vc4_irq_uninstall(struct drm_device *dev)
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{
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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/* Disable sending interrupts for our driver's IRQs. */
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V3D_WRITE(V3D_INTDIS, V3D_DRIVER_IRQS);
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/* Clear any pending interrupts we might have left. */
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V3D_WRITE(V3D_INTCTL, V3D_DRIVER_IRQS);
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/* Finish any interrupt handler still in flight. */
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disable_irq(dev->irq);
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cancel_work_sync(&vc4->overflow_mem_work);
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}
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/** Reinitializes interrupt registers when a GPU reset is performed. */
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void vc4_irq_reset(struct drm_device *dev)
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{
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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unsigned long irqflags;
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/* Acknowledge any stale IRQs. */
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V3D_WRITE(V3D_INTCTL, V3D_DRIVER_IRQS);
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/*
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* Turn all our interrupts on. Binner out of memory is the
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* only one we expect to trigger at this point, since we've
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* just come from poweron and haven't supplied any overflow
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* memory yet.
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*/
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V3D_WRITE(V3D_INTENA, V3D_DRIVER_IRQS);
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spin_lock_irqsave(&vc4->job_lock, irqflags);
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vc4_cancel_bin_job(dev);
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vc4_irq_finish_render_job(dev);
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spin_unlock_irqrestore(&vc4->job_lock, irqflags);
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}
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