![Eric Anholt](/assets/img/avatar_default.png)
This is useful to allow GL to provide defined results for overlapping glBlitFramebuffer, which X11 in turn uses to accelerate uncomposited window movement without first blitting to a temporary. x11perf -copywinwin100 goes from 1850/sec to 4850/sec. v2: Default to the same behavior as before when the flags aren't passed. (suggested by Boris) Signed-off-by: Eric Anholt <eric@anholt.net> Link: https://patchwork.freedesktop.org/patch/msgid/20170725162733.28007-2-eric@anholt.net Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
662 lines
19 KiB
C
662 lines
19 KiB
C
/*
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* Copyright © 2014-2015 Broadcom
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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/**
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* DOC: Render command list generation
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*
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* In the V3D hardware, render command lists are what load and store
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* tiles of a framebuffer and optionally call out to binner-generated
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* command lists to do the 3D drawing for that tile.
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*
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* In the VC4 driver, render command list generation is performed by the
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* kernel instead of userspace. We do this because validating a
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* user-submitted command list is hard to get right and has high CPU overhead,
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* while the number of valid configurations for render command lists is
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* actually fairly low.
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*/
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#include "uapi/drm/vc4_drm.h"
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#include "vc4_drv.h"
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#include "vc4_packet.h"
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struct vc4_rcl_setup {
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struct drm_gem_cma_object *color_read;
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struct drm_gem_cma_object *color_write;
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struct drm_gem_cma_object *zs_read;
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struct drm_gem_cma_object *zs_write;
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struct drm_gem_cma_object *msaa_color_write;
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struct drm_gem_cma_object *msaa_zs_write;
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struct drm_gem_cma_object *rcl;
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u32 next_offset;
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u32 next_write_bo_index;
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};
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static inline void rcl_u8(struct vc4_rcl_setup *setup, u8 val)
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{
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*(u8 *)(setup->rcl->vaddr + setup->next_offset) = val;
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setup->next_offset += 1;
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}
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static inline void rcl_u16(struct vc4_rcl_setup *setup, u16 val)
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{
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*(u16 *)(setup->rcl->vaddr + setup->next_offset) = val;
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setup->next_offset += 2;
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}
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static inline void rcl_u32(struct vc4_rcl_setup *setup, u32 val)
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{
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*(u32 *)(setup->rcl->vaddr + setup->next_offset) = val;
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setup->next_offset += 4;
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}
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/*
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* Emits a no-op STORE_TILE_BUFFER_GENERAL.
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*
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* If we emit a PACKET_TILE_COORDINATES, it must be followed by a store of
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* some sort before another load is triggered.
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*/
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static void vc4_store_before_load(struct vc4_rcl_setup *setup)
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{
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rcl_u8(setup, VC4_PACKET_STORE_TILE_BUFFER_GENERAL);
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rcl_u16(setup,
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VC4_SET_FIELD(VC4_LOADSTORE_TILE_BUFFER_NONE,
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VC4_LOADSTORE_TILE_BUFFER_BUFFER) |
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VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR |
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VC4_STORE_TILE_BUFFER_DISABLE_ZS_CLEAR |
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VC4_STORE_TILE_BUFFER_DISABLE_VG_MASK_CLEAR);
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rcl_u32(setup, 0); /* no address, since we're in None mode */
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}
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/*
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* Calculates the physical address of the start of a tile in a RCL surface.
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*
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* Unlike the other load/store packets,
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* VC4_PACKET_LOAD/STORE_FULL_RES_TILE_BUFFER don't look at the tile
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* coordinates packet, and instead just store to the address given.
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*/
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static uint32_t vc4_full_res_offset(struct vc4_exec_info *exec,
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struct drm_gem_cma_object *bo,
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struct drm_vc4_submit_rcl_surface *surf,
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uint8_t x, uint8_t y)
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{
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return bo->paddr + surf->offset + VC4_TILE_BUFFER_SIZE *
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(DIV_ROUND_UP(exec->args->width, 32) * y + x);
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}
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/*
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* Emits a PACKET_TILE_COORDINATES if one isn't already pending.
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*
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* The tile coordinates packet triggers a pending load if there is one, are
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* used for clipping during rendering, and determine where loads/stores happen
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* relative to their base address.
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*/
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static void vc4_tile_coordinates(struct vc4_rcl_setup *setup,
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uint32_t x, uint32_t y)
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{
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rcl_u8(setup, VC4_PACKET_TILE_COORDINATES);
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rcl_u8(setup, x);
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rcl_u8(setup, y);
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}
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static void emit_tile(struct vc4_exec_info *exec,
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struct vc4_rcl_setup *setup,
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uint8_t x, uint8_t y, bool first, bool last)
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{
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struct drm_vc4_submit_cl *args = exec->args;
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bool has_bin = args->bin_cl_size != 0;
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/* Note that the load doesn't actually occur until the
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* tile coords packet is processed, and only one load
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* may be outstanding at a time.
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*/
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if (setup->color_read) {
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if (args->color_read.flags &
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VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) {
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rcl_u8(setup, VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER);
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rcl_u32(setup,
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vc4_full_res_offset(exec, setup->color_read,
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&args->color_read, x, y) |
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VC4_LOADSTORE_FULL_RES_DISABLE_ZS);
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} else {
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rcl_u8(setup, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL);
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rcl_u16(setup, args->color_read.bits);
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rcl_u32(setup, setup->color_read->paddr +
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args->color_read.offset);
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}
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}
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if (setup->zs_read) {
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if (args->zs_read.flags &
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VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) {
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rcl_u8(setup, VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER);
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rcl_u32(setup,
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vc4_full_res_offset(exec, setup->zs_read,
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&args->zs_read, x, y) |
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VC4_LOADSTORE_FULL_RES_DISABLE_COLOR);
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} else {
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if (setup->color_read) {
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/* Exec previous load. */
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vc4_tile_coordinates(setup, x, y);
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vc4_store_before_load(setup);
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}
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rcl_u8(setup, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL);
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rcl_u16(setup, args->zs_read.bits);
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rcl_u32(setup, setup->zs_read->paddr +
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args->zs_read.offset);
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}
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}
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/* Clipping depends on tile coordinates having been
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* emitted, so we always need one here.
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*/
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vc4_tile_coordinates(setup, x, y);
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/* Wait for the binner before jumping to the first
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* tile's lists.
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*/
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if (first && has_bin)
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rcl_u8(setup, VC4_PACKET_WAIT_ON_SEMAPHORE);
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if (has_bin) {
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rcl_u8(setup, VC4_PACKET_BRANCH_TO_SUB_LIST);
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rcl_u32(setup, (exec->tile_alloc_offset +
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(y * exec->bin_tiles_x + x) * 32));
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}
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if (setup->msaa_color_write) {
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bool last_tile_write = (!setup->msaa_zs_write &&
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!setup->zs_write &&
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!setup->color_write);
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uint32_t bits = VC4_LOADSTORE_FULL_RES_DISABLE_ZS;
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if (!last_tile_write)
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bits |= VC4_LOADSTORE_FULL_RES_DISABLE_CLEAR_ALL;
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else if (last)
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bits |= VC4_LOADSTORE_FULL_RES_EOF;
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rcl_u8(setup, VC4_PACKET_STORE_FULL_RES_TILE_BUFFER);
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rcl_u32(setup,
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vc4_full_res_offset(exec, setup->msaa_color_write,
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&args->msaa_color_write, x, y) |
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bits);
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}
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if (setup->msaa_zs_write) {
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bool last_tile_write = (!setup->zs_write &&
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!setup->color_write);
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uint32_t bits = VC4_LOADSTORE_FULL_RES_DISABLE_COLOR;
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if (setup->msaa_color_write)
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vc4_tile_coordinates(setup, x, y);
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if (!last_tile_write)
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bits |= VC4_LOADSTORE_FULL_RES_DISABLE_CLEAR_ALL;
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else if (last)
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bits |= VC4_LOADSTORE_FULL_RES_EOF;
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rcl_u8(setup, VC4_PACKET_STORE_FULL_RES_TILE_BUFFER);
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rcl_u32(setup,
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vc4_full_res_offset(exec, setup->msaa_zs_write,
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&args->msaa_zs_write, x, y) |
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bits);
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}
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if (setup->zs_write) {
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bool last_tile_write = !setup->color_write;
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if (setup->msaa_color_write || setup->msaa_zs_write)
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vc4_tile_coordinates(setup, x, y);
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rcl_u8(setup, VC4_PACKET_STORE_TILE_BUFFER_GENERAL);
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rcl_u16(setup, args->zs_write.bits |
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(last_tile_write ?
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0 : VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR));
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rcl_u32(setup,
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(setup->zs_write->paddr + args->zs_write.offset) |
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((last && last_tile_write) ?
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VC4_LOADSTORE_TILE_BUFFER_EOF : 0));
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}
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if (setup->color_write) {
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if (setup->msaa_color_write || setup->msaa_zs_write ||
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setup->zs_write) {
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vc4_tile_coordinates(setup, x, y);
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}
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if (last)
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rcl_u8(setup, VC4_PACKET_STORE_MS_TILE_BUFFER_AND_EOF);
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else
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rcl_u8(setup, VC4_PACKET_STORE_MS_TILE_BUFFER);
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}
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}
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static int vc4_create_rcl_bo(struct drm_device *dev, struct vc4_exec_info *exec,
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struct vc4_rcl_setup *setup)
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{
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struct drm_vc4_submit_cl *args = exec->args;
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bool has_bin = args->bin_cl_size != 0;
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uint8_t min_x_tile = args->min_x_tile;
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uint8_t min_y_tile = args->min_y_tile;
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uint8_t max_x_tile = args->max_x_tile;
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uint8_t max_y_tile = args->max_y_tile;
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uint8_t xtiles = max_x_tile - min_x_tile + 1;
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uint8_t ytiles = max_y_tile - min_y_tile + 1;
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uint8_t xi, yi;
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uint32_t size, loop_body_size;
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bool positive_x = true;
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bool positive_y = true;
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if (args->flags & VC4_SUBMIT_CL_FIXED_RCL_ORDER) {
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if (!(args->flags & VC4_SUBMIT_CL_RCL_ORDER_INCREASING_X))
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positive_x = false;
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if (!(args->flags & VC4_SUBMIT_CL_RCL_ORDER_INCREASING_Y))
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positive_y = false;
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}
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size = VC4_PACKET_TILE_RENDERING_MODE_CONFIG_SIZE;
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loop_body_size = VC4_PACKET_TILE_COORDINATES_SIZE;
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if (args->flags & VC4_SUBMIT_CL_USE_CLEAR_COLOR) {
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size += VC4_PACKET_CLEAR_COLORS_SIZE +
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VC4_PACKET_TILE_COORDINATES_SIZE +
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VC4_PACKET_STORE_TILE_BUFFER_GENERAL_SIZE;
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}
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if (setup->color_read) {
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if (args->color_read.flags &
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VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) {
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loop_body_size += VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER_SIZE;
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} else {
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loop_body_size += VC4_PACKET_LOAD_TILE_BUFFER_GENERAL_SIZE;
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}
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}
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if (setup->zs_read) {
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if (args->zs_read.flags &
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VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) {
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loop_body_size += VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER_SIZE;
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} else {
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if (setup->color_read &&
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!(args->color_read.flags &
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VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES)) {
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loop_body_size += VC4_PACKET_TILE_COORDINATES_SIZE;
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loop_body_size += VC4_PACKET_STORE_TILE_BUFFER_GENERAL_SIZE;
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}
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loop_body_size += VC4_PACKET_LOAD_TILE_BUFFER_GENERAL_SIZE;
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}
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}
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if (has_bin) {
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size += VC4_PACKET_WAIT_ON_SEMAPHORE_SIZE;
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loop_body_size += VC4_PACKET_BRANCH_TO_SUB_LIST_SIZE;
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}
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if (setup->msaa_color_write)
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loop_body_size += VC4_PACKET_STORE_FULL_RES_TILE_BUFFER_SIZE;
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if (setup->msaa_zs_write)
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loop_body_size += VC4_PACKET_STORE_FULL_RES_TILE_BUFFER_SIZE;
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if (setup->zs_write)
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loop_body_size += VC4_PACKET_STORE_TILE_BUFFER_GENERAL_SIZE;
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if (setup->color_write)
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loop_body_size += VC4_PACKET_STORE_MS_TILE_BUFFER_SIZE;
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/* We need a VC4_PACKET_TILE_COORDINATES in between each store. */
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loop_body_size += VC4_PACKET_TILE_COORDINATES_SIZE *
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((setup->msaa_color_write != NULL) +
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(setup->msaa_zs_write != NULL) +
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(setup->color_write != NULL) +
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(setup->zs_write != NULL) - 1);
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size += xtiles * ytiles * loop_body_size;
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setup->rcl = &vc4_bo_create(dev, size, true, VC4_BO_TYPE_RCL)->base;
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if (IS_ERR(setup->rcl))
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return PTR_ERR(setup->rcl);
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list_add_tail(&to_vc4_bo(&setup->rcl->base)->unref_head,
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&exec->unref_list);
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/* The tile buffer gets cleared when the previous tile is stored. If
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* the clear values changed between frames, then the tile buffer has
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* stale clear values in it, so we have to do a store in None mode (no
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* writes) so that we trigger the tile buffer clear.
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*/
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if (args->flags & VC4_SUBMIT_CL_USE_CLEAR_COLOR) {
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rcl_u8(setup, VC4_PACKET_CLEAR_COLORS);
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rcl_u32(setup, args->clear_color[0]);
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rcl_u32(setup, args->clear_color[1]);
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rcl_u32(setup, args->clear_z);
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rcl_u8(setup, args->clear_s);
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vc4_tile_coordinates(setup, 0, 0);
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rcl_u8(setup, VC4_PACKET_STORE_TILE_BUFFER_GENERAL);
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rcl_u16(setup, VC4_LOADSTORE_TILE_BUFFER_NONE);
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rcl_u32(setup, 0); /* no address, since we're in None mode */
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}
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rcl_u8(setup, VC4_PACKET_TILE_RENDERING_MODE_CONFIG);
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rcl_u32(setup,
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(setup->color_write ? (setup->color_write->paddr +
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args->color_write.offset) :
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0));
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rcl_u16(setup, args->width);
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rcl_u16(setup, args->height);
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rcl_u16(setup, args->color_write.bits);
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for (yi = 0; yi < ytiles; yi++) {
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int y = positive_y ? min_y_tile + yi : max_y_tile - yi;
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for (xi = 0; xi < xtiles; xi++) {
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int x = positive_x ? min_x_tile + xi : max_x_tile - xi;
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bool first = (xi == 0 && yi == 0);
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bool last = (xi == xtiles - 1 && yi == ytiles - 1);
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emit_tile(exec, setup, x, y, first, last);
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}
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}
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BUG_ON(setup->next_offset != size);
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exec->ct1ca = setup->rcl->paddr;
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exec->ct1ea = setup->rcl->paddr + setup->next_offset;
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return 0;
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}
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static int vc4_full_res_bounds_check(struct vc4_exec_info *exec,
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struct drm_gem_cma_object *obj,
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struct drm_vc4_submit_rcl_surface *surf)
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{
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struct drm_vc4_submit_cl *args = exec->args;
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u32 render_tiles_stride = DIV_ROUND_UP(exec->args->width, 32);
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if (surf->offset > obj->base.size) {
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DRM_DEBUG("surface offset %d > BO size %zd\n",
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surf->offset, obj->base.size);
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return -EINVAL;
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}
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if ((obj->base.size - surf->offset) / VC4_TILE_BUFFER_SIZE <
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render_tiles_stride * args->max_y_tile + args->max_x_tile) {
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DRM_DEBUG("MSAA tile %d, %d out of bounds "
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"(bo size %zd, offset %d).\n",
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args->max_x_tile, args->max_y_tile,
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obj->base.size,
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surf->offset);
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return -EINVAL;
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}
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return 0;
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}
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static int vc4_rcl_msaa_surface_setup(struct vc4_exec_info *exec,
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struct drm_gem_cma_object **obj,
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struct drm_vc4_submit_rcl_surface *surf)
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{
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if (surf->flags != 0 || surf->bits != 0) {
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DRM_DEBUG("MSAA surface had nonzero flags/bits\n");
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return -EINVAL;
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}
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if (surf->hindex == ~0)
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return 0;
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*obj = vc4_use_bo(exec, surf->hindex);
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if (!*obj)
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return -EINVAL;
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exec->rcl_write_bo[exec->rcl_write_bo_count++] = *obj;
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|
|
if (surf->offset & 0xf) {
|
|
DRM_DEBUG("MSAA write must be 16b aligned.\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
return vc4_full_res_bounds_check(exec, *obj, surf);
|
|
}
|
|
|
|
static int vc4_rcl_surface_setup(struct vc4_exec_info *exec,
|
|
struct drm_gem_cma_object **obj,
|
|
struct drm_vc4_submit_rcl_surface *surf,
|
|
bool is_write)
|
|
{
|
|
uint8_t tiling = VC4_GET_FIELD(surf->bits,
|
|
VC4_LOADSTORE_TILE_BUFFER_TILING);
|
|
uint8_t buffer = VC4_GET_FIELD(surf->bits,
|
|
VC4_LOADSTORE_TILE_BUFFER_BUFFER);
|
|
uint8_t format = VC4_GET_FIELD(surf->bits,
|
|
VC4_LOADSTORE_TILE_BUFFER_FORMAT);
|
|
int cpp;
|
|
int ret;
|
|
|
|
if (surf->flags & ~VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) {
|
|
DRM_DEBUG("Extra flags set\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (surf->hindex == ~0)
|
|
return 0;
|
|
|
|
*obj = vc4_use_bo(exec, surf->hindex);
|
|
if (!*obj)
|
|
return -EINVAL;
|
|
|
|
if (is_write)
|
|
exec->rcl_write_bo[exec->rcl_write_bo_count++] = *obj;
|
|
|
|
if (surf->flags & VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) {
|
|
if (surf == &exec->args->zs_write) {
|
|
DRM_DEBUG("general zs write may not be a full-res.\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (surf->bits != 0) {
|
|
DRM_DEBUG("load/store general bits set with "
|
|
"full res load/store.\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
ret = vc4_full_res_bounds_check(exec, *obj, surf);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
if (surf->bits & ~(VC4_LOADSTORE_TILE_BUFFER_TILING_MASK |
|
|
VC4_LOADSTORE_TILE_BUFFER_BUFFER_MASK |
|
|
VC4_LOADSTORE_TILE_BUFFER_FORMAT_MASK)) {
|
|
DRM_DEBUG("Unknown bits in load/store: 0x%04x\n",
|
|
surf->bits);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (tiling > VC4_TILING_FORMAT_LT) {
|
|
DRM_DEBUG("Bad tiling format\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (buffer == VC4_LOADSTORE_TILE_BUFFER_ZS) {
|
|
if (format != 0) {
|
|
DRM_DEBUG("No color format should be set for ZS\n");
|
|
return -EINVAL;
|
|
}
|
|
cpp = 4;
|
|
} else if (buffer == VC4_LOADSTORE_TILE_BUFFER_COLOR) {
|
|
switch (format) {
|
|
case VC4_LOADSTORE_TILE_BUFFER_BGR565:
|
|
case VC4_LOADSTORE_TILE_BUFFER_BGR565_DITHER:
|
|
cpp = 2;
|
|
break;
|
|
case VC4_LOADSTORE_TILE_BUFFER_RGBA8888:
|
|
cpp = 4;
|
|
break;
|
|
default:
|
|
DRM_DEBUG("Bad tile buffer format\n");
|
|
return -EINVAL;
|
|
}
|
|
} else {
|
|
DRM_DEBUG("Bad load/store buffer %d.\n", buffer);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (surf->offset & 0xf) {
|
|
DRM_DEBUG("load/store buffer must be 16b aligned.\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (!vc4_check_tex_size(exec, *obj, surf->offset, tiling,
|
|
exec->args->width, exec->args->height, cpp)) {
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
vc4_rcl_render_config_surface_setup(struct vc4_exec_info *exec,
|
|
struct vc4_rcl_setup *setup,
|
|
struct drm_gem_cma_object **obj,
|
|
struct drm_vc4_submit_rcl_surface *surf)
|
|
{
|
|
uint8_t tiling = VC4_GET_FIELD(surf->bits,
|
|
VC4_RENDER_CONFIG_MEMORY_FORMAT);
|
|
uint8_t format = VC4_GET_FIELD(surf->bits,
|
|
VC4_RENDER_CONFIG_FORMAT);
|
|
int cpp;
|
|
|
|
if (surf->flags != 0) {
|
|
DRM_DEBUG("No flags supported on render config.\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (surf->bits & ~(VC4_RENDER_CONFIG_MEMORY_FORMAT_MASK |
|
|
VC4_RENDER_CONFIG_FORMAT_MASK |
|
|
VC4_RENDER_CONFIG_MS_MODE_4X |
|
|
VC4_RENDER_CONFIG_DECIMATE_MODE_4X)) {
|
|
DRM_DEBUG("Unknown bits in render config: 0x%04x\n",
|
|
surf->bits);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (surf->hindex == ~0)
|
|
return 0;
|
|
|
|
*obj = vc4_use_bo(exec, surf->hindex);
|
|
if (!*obj)
|
|
return -EINVAL;
|
|
|
|
exec->rcl_write_bo[exec->rcl_write_bo_count++] = *obj;
|
|
|
|
if (tiling > VC4_TILING_FORMAT_LT) {
|
|
DRM_DEBUG("Bad tiling format\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
switch (format) {
|
|
case VC4_RENDER_CONFIG_FORMAT_BGR565_DITHERED:
|
|
case VC4_RENDER_CONFIG_FORMAT_BGR565:
|
|
cpp = 2;
|
|
break;
|
|
case VC4_RENDER_CONFIG_FORMAT_RGBA8888:
|
|
cpp = 4;
|
|
break;
|
|
default:
|
|
DRM_DEBUG("Bad tile buffer format\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (!vc4_check_tex_size(exec, *obj, surf->offset, tiling,
|
|
exec->args->width, exec->args->height, cpp)) {
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec)
|
|
{
|
|
struct vc4_rcl_setup setup = {0};
|
|
struct drm_vc4_submit_cl *args = exec->args;
|
|
bool has_bin = args->bin_cl_size != 0;
|
|
int ret;
|
|
|
|
if (args->min_x_tile > args->max_x_tile ||
|
|
args->min_y_tile > args->max_y_tile) {
|
|
DRM_DEBUG("Bad render tile set (%d,%d)-(%d,%d)\n",
|
|
args->min_x_tile, args->min_y_tile,
|
|
args->max_x_tile, args->max_y_tile);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (has_bin &&
|
|
(args->max_x_tile > exec->bin_tiles_x ||
|
|
args->max_y_tile > exec->bin_tiles_y)) {
|
|
DRM_DEBUG("Render tiles (%d,%d) outside of bin config "
|
|
"(%d,%d)\n",
|
|
args->max_x_tile, args->max_y_tile,
|
|
exec->bin_tiles_x, exec->bin_tiles_y);
|
|
return -EINVAL;
|
|
}
|
|
|
|
ret = vc4_rcl_render_config_surface_setup(exec, &setup,
|
|
&setup.color_write,
|
|
&args->color_write);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = vc4_rcl_surface_setup(exec, &setup.color_read, &args->color_read,
|
|
false);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = vc4_rcl_surface_setup(exec, &setup.zs_read, &args->zs_read,
|
|
false);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = vc4_rcl_surface_setup(exec, &setup.zs_write, &args->zs_write,
|
|
true);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = vc4_rcl_msaa_surface_setup(exec, &setup.msaa_color_write,
|
|
&args->msaa_color_write);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = vc4_rcl_msaa_surface_setup(exec, &setup.msaa_zs_write,
|
|
&args->msaa_zs_write);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* We shouldn't even have the job submitted to us if there's no
|
|
* surface to write out.
|
|
*/
|
|
if (!setup.color_write && !setup.zs_write &&
|
|
!setup.msaa_color_write && !setup.msaa_zs_write) {
|
|
DRM_DEBUG("RCL requires color or Z/S write\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
return vc4_create_rcl_bo(dev, exec, &setup);
|
|
}
|