da11195779
If we have two cache events that require different settings of the L2SEL bits in MMCR1 then we can not schedule those events simultaneously. Add logic to the constraint handling to express that. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> |
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| .. | ||
| Makefile | ||
| callchain.c | ||
| core-book3s.c | ||
| core-fsl-emb.c | ||
| e500-pmu.c | ||
| mpc7450-pmu.c | ||
| power4-pmu.c | ||
| power5+-pmu.c | ||
| power5-pmu.c | ||
| power6-pmu.c | ||
| power7-pmu.c | ||
| ppc970-pmu.c | ||