348 lines
9.1 KiB
C
348 lines
9.1 KiB
C
/*
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* Copyright (C) 2000-2002 Mark Lord <mlord@pobox.com>
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* Copyright (C) 2007 Bartlomiej Zolnierkiewicz
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*
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* May be copied or modified under the terms of the GNU General Public License
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*
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* Development of this chipset driver was funded
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* by the nice folks at National Semiconductor.
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*
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* Documentation:
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* Available from National Semiconductor
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*/
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/hdreg.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/ide.h>
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#include <linux/pm.h>
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#include <asm/io.h>
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#define SC1200_REV_A 0x00
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#define SC1200_REV_B1 0x01
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#define SC1200_REV_B3 0x02
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#define SC1200_REV_C1 0x03
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#define SC1200_REV_D1 0x04
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#define PCI_CLK_33 0x00
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#define PCI_CLK_48 0x01
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#define PCI_CLK_66 0x02
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#define PCI_CLK_33A 0x03
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static unsigned short sc1200_get_pci_clock (void)
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{
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unsigned char chip_id, silicon_revision;
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unsigned int pci_clock;
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/*
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* Check the silicon revision, as not all versions of the chip
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* have the register with the fast PCI bus timings.
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*/
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chip_id = inb (0x903c);
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silicon_revision = inb (0x903d);
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// Read the fast pci clock frequency
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if (chip_id == 0x04 && silicon_revision < SC1200_REV_B1) {
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pci_clock = PCI_CLK_33;
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} else {
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// check clock generator configuration (cfcc)
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// the clock is in bits 8 and 9 of this word
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pci_clock = inw (0x901e);
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pci_clock >>= 8;
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pci_clock &= 0x03;
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if (pci_clock == PCI_CLK_33A)
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pci_clock = PCI_CLK_33;
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}
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return pci_clock;
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}
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/*
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* Here are the standard PIO mode 0-4 timings for each "format".
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* Format-0 uses fast data reg timings, with slower command reg timings.
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* Format-1 uses fast timings for all registers, but won't work with all drives.
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*/
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static const unsigned int sc1200_pio_timings[4][5] =
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{{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010}, // format0 33Mhz
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{0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}, // format1, 33Mhz
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{0xfaa3f4f3, 0xc23232b2, 0x513101c1, 0x31213121, 0x10211021}, // format1, 48Mhz
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{0xfff4fff4, 0xf35353d3, 0x814102f1, 0x42314231, 0x11311131}}; // format1, 66Mhz
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/*
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* After chip reset, the PIO timings are set to 0x00009172, which is not valid.
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*/
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//#define SC1200_BAD_PIO(timings) (((timings)&~0x80000000)==0x00009172)
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static void sc1200_tunepio(ide_drive_t *drive, u8 pio)
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{
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ide_hwif_t *hwif = drive->hwif;
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struct pci_dev *pdev = to_pci_dev(hwif->dev);
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unsigned int basereg = hwif->channel ? 0x50 : 0x40, format = 0;
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pci_read_config_dword(pdev, basereg + 4, &format);
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format = (format >> 31) & 1;
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if (format)
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format += sc1200_get_pci_clock();
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pci_write_config_dword(pdev, basereg + ((drive->dn & 1) << 3),
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sc1200_pio_timings[format][pio]);
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}
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/*
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* The SC1200 specifies that two drives sharing a cable cannot mix
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* UDMA/MDMA. It has to be one or the other, for the pair, though
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* different timings can still be chosen for each drive. We could
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* set the appropriate timing bits on the fly, but that might be
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* a bit confusing. So, for now we statically handle this requirement
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* by looking at our mate drive to see what it is capable of, before
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* choosing a mode for our own drive.
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*/
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static u8 sc1200_udma_filter(ide_drive_t *drive)
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{
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ide_hwif_t *hwif = drive->hwif;
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ide_drive_t *mate = &hwif->drives[(drive->dn & 1) ^ 1];
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struct hd_driveid *mateid = mate->id;
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u8 mask = hwif->ultra_mask;
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if (mate->present == 0)
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goto out;
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if ((mateid->capability & 1) && __ide_dma_bad_drive(mate) == 0) {
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if ((mateid->field_valid & 4) && (mateid->dma_ultra & 7))
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goto out;
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if ((mateid->field_valid & 2) && (mateid->dma_mword & 7))
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mask = 0;
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}
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out:
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return mask;
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}
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static void sc1200_set_dma_mode(ide_drive_t *drive, const u8 mode)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct pci_dev *dev = to_pci_dev(hwif->dev);
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int unit = drive->select.b.unit;
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unsigned int reg, timings;
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unsigned short pci_clock;
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unsigned int basereg = hwif->channel ? 0x50 : 0x40;
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static const u32 udma_timing[3][3] = {
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{ 0x00921250, 0x00911140, 0x00911030 },
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{ 0x00932470, 0x00922260, 0x00922140 },
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{ 0x009436a1, 0x00933481, 0x00923261 },
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};
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static const u32 mwdma_timing[3][3] = {
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{ 0x00077771, 0x00012121, 0x00002020 },
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{ 0x000bbbb2, 0x00024241, 0x00013131 },
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{ 0x000ffff3, 0x00035352, 0x00015151 },
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};
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pci_clock = sc1200_get_pci_clock();
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/*
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* Note that each DMA mode has several timings associated with it.
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* The correct timing depends on the fast PCI clock freq.
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*/
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if (mode >= XFER_UDMA_0)
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timings = udma_timing[pci_clock][mode - XFER_UDMA_0];
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else
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timings = mwdma_timing[pci_clock][mode - XFER_MW_DMA_0];
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if (unit == 0) { /* are we configuring drive0? */
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pci_read_config_dword(dev, basereg + 4, ®);
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timings |= reg & 0x80000000; /* preserve PIO format bit */
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pci_write_config_dword(dev, basereg + 4, timings);
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} else
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pci_write_config_dword(dev, basereg + 12, timings);
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}
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/* Replacement for the standard ide_dma_end action in
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* dma_proc.
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*
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* returns 1 on error, 0 otherwise
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*/
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static int sc1200_ide_dma_end (ide_drive_t *drive)
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{
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ide_hwif_t *hwif = HWIF(drive);
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unsigned long dma_base = hwif->dma_base;
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byte dma_stat;
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dma_stat = inb(dma_base+2); /* get DMA status */
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if (!(dma_stat & 4))
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printk(" ide_dma_end dma_stat=%0x err=%x newerr=%x\n",
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dma_stat, ((dma_stat&7)!=4), ((dma_stat&2)==2));
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outb(dma_stat|0x1b, dma_base+2); /* clear the INTR & ERROR bits */
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outb(inb(dma_base)&~1, dma_base); /* !! DO THIS HERE !! stop DMA */
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drive->waiting_for_dma = 0;
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ide_destroy_dmatable(drive); /* purge DMA mappings */
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return (dma_stat & 7) != 4; /* verify good DMA status */
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}
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/*
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* sc1200_set_pio_mode() handles setting of PIO modes
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* for both the chipset and drive.
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*
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* All existing BIOSs for this chipset guarantee that all drives
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* will have valid default PIO timings set up before we get here.
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*/
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static void sc1200_set_pio_mode(ide_drive_t *drive, const u8 pio)
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{
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ide_hwif_t *hwif = HWIF(drive);
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int mode = -1;
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/*
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* bad abuse of ->set_pio_mode interface
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*/
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switch (pio) {
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case 200: mode = XFER_UDMA_0; break;
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case 201: mode = XFER_UDMA_1; break;
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case 202: mode = XFER_UDMA_2; break;
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case 100: mode = XFER_MW_DMA_0; break;
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case 101: mode = XFER_MW_DMA_1; break;
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case 102: mode = XFER_MW_DMA_2; break;
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}
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if (mode != -1) {
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printk("SC1200: %s: changing (U)DMA mode\n", drive->name);
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ide_dma_off_quietly(drive);
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if (ide_set_dma_mode(drive, mode) == 0 && drive->using_dma)
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hwif->dma_host_set(drive, 1);
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return;
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}
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sc1200_tunepio(drive, pio);
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}
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#ifdef CONFIG_PM
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struct sc1200_saved_state {
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u32 regs[8];
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};
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static int sc1200_suspend (struct pci_dev *dev, pm_message_t state)
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{
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printk("SC1200: suspend(%u)\n", state.event);
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/*
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* we only save state when going from full power to less
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*/
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if (state.event == PM_EVENT_ON) {
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struct sc1200_saved_state *ss;
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unsigned int r;
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/*
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* allocate a permanent save area, if not already allocated
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*/
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ss = (struct sc1200_saved_state *)pci_get_drvdata(dev);
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if (ss == NULL) {
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ss = kmalloc(sizeof(*ss), GFP_KERNEL);
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if (ss == NULL)
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return -ENOMEM;
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pci_set_drvdata(dev, ss);
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}
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/*
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* save timing registers
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* (this may be unnecessary if BIOS also does it)
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*/
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for (r = 0; r < 8; r++)
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pci_read_config_dword(dev, 0x40 + r * 4, &ss->regs[r]);
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}
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pci_disable_device(dev);
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pci_set_power_state(dev, pci_choose_state(dev, state));
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return 0;
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}
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static int sc1200_resume (struct pci_dev *dev)
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{
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struct sc1200_saved_state *ss;
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unsigned int r;
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int i;
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i = pci_enable_device(dev);
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if (i)
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return i;
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ss = (struct sc1200_saved_state *)pci_get_drvdata(dev);
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/*
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* restore timing registers
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* (this may be unnecessary if BIOS also does it)
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*/
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if (ss) {
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for (r = 0; r < 8; r++)
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pci_write_config_dword(dev, 0x40 + r * 4, ss->regs[r]);
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}
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return 0;
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}
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#endif
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/*
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* This gets invoked by the IDE driver once for each channel,
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* and performs channel-specific pre-initialization before drive probing.
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*/
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static void __devinit init_hwif_sc1200 (ide_hwif_t *hwif)
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{
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hwif->set_pio_mode = &sc1200_set_pio_mode;
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hwif->set_dma_mode = &sc1200_set_dma_mode;
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if (hwif->dma_base == 0)
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return;
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hwif->udma_filter = sc1200_udma_filter;
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hwif->ide_dma_end = &sc1200_ide_dma_end;
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}
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static const struct ide_port_info sc1200_chipset __devinitdata = {
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.name = "SC1200",
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.init_hwif = init_hwif_sc1200,
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.host_flags = IDE_HFLAG_SERIALIZE |
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IDE_HFLAG_POST_SET_MODE |
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IDE_HFLAG_ABUSE_DMA_MODES |
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IDE_HFLAG_BOOTABLE,
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.pio_mask = ATA_PIO4,
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.mwdma_mask = ATA_MWDMA2,
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.udma_mask = ATA_UDMA2,
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};
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static int __devinit sc1200_init_one(struct pci_dev *dev, const struct pci_device_id *id)
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{
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return ide_setup_pci_device(dev, &sc1200_chipset);
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}
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static const struct pci_device_id sc1200_pci_tbl[] = {
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{ PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_SCx200_IDE), 0},
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{ 0, },
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};
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MODULE_DEVICE_TABLE(pci, sc1200_pci_tbl);
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static struct pci_driver driver = {
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.name = "SC1200_IDE",
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.id_table = sc1200_pci_tbl,
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.probe = sc1200_init_one,
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#ifdef CONFIG_PM
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.suspend = sc1200_suspend,
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.resume = sc1200_resume,
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#endif
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};
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static int __init sc1200_ide_init(void)
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{
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return ide_pci_register_driver(&driver);
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}
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module_init(sc1200_ide_init);
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MODULE_AUTHOR("Mark Lord");
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MODULE_DESCRIPTION("PCI driver module for NS SC1200 IDE");
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MODULE_LICENSE("GPL");
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