![Ralf Baechle](/assets/img/avatar_default.png)
They tend to get not updated when files are moved around or copied and lack any obvious use. While at it zap some only too obvious comments and as per Shinya's suggestion, add a copyright header to extable.c. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Acked-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com> Acked-by: Thadeu Lima de Souza Cascardo <cascardo@holoscopio.com>
279 lines
7.5 KiB
C
279 lines
7.5 KiB
C
/*
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* Bus error event handling code for systems equipped with ECC
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* handling logic, i.e. DECstation/DECsystem 5000/200 (KN02),
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* 5000/240 (KN03), 5000/260 (KN05) and DECsystem 5900 (KN03),
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* 5900/260 (KN05) systems.
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*
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* Copyright (c) 2003, 2005 Maciej W. Rozycki
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/types.h>
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#include <asm/addrspace.h>
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#include <asm/bootinfo.h>
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#include <asm/cpu.h>
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#include <asm/irq_regs.h>
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#include <asm/processor.h>
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#include <asm/ptrace.h>
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#include <asm/system.h>
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#include <asm/traps.h>
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#include <asm/dec/ecc.h>
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#include <asm/dec/kn02.h>
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#include <asm/dec/kn03.h>
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#include <asm/dec/kn05.h>
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static volatile u32 *kn0x_erraddr;
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static volatile u32 *kn0x_chksyn;
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static inline void dec_ecc_be_ack(void)
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{
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*kn0x_erraddr = 0; /* any write clears the IRQ */
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iob();
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}
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static int dec_ecc_be_backend(struct pt_regs *regs, int is_fixup, int invoker)
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{
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static const char excstr[] = "exception";
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static const char intstr[] = "interrupt";
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static const char cpustr[] = "CPU";
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static const char dmastr[] = "DMA";
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static const char readstr[] = "read";
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static const char mreadstr[] = "memory read";
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static const char writestr[] = "write";
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static const char mwritstr[] = "partial memory write";
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static const char timestr[] = "timeout";
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static const char overstr[] = "overrun";
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static const char eccstr[] = "ECC error";
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const char *kind, *agent, *cycle, *event;
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const char *status = "", *xbit = "", *fmt = "";
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unsigned long address;
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u16 syn = 0, sngl;
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int i = 0;
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u32 erraddr = *kn0x_erraddr;
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u32 chksyn = *kn0x_chksyn;
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int action = MIPS_BE_FATAL;
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/* For non-ECC ack ASAP, so that any subsequent errors get caught. */
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if ((erraddr & (KN0X_EAR_VALID | KN0X_EAR_ECCERR)) == KN0X_EAR_VALID)
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dec_ecc_be_ack();
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kind = invoker ? intstr : excstr;
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if (!(erraddr & KN0X_EAR_VALID)) {
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/* No idea what happened. */
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printk(KERN_ALERT "Unidentified bus error %s\n", kind);
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return action;
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}
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agent = (erraddr & KN0X_EAR_CPU) ? cpustr : dmastr;
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if (erraddr & KN0X_EAR_ECCERR) {
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/* An ECC error on a CPU or DMA transaction. */
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cycle = (erraddr & KN0X_EAR_WRITE) ? mwritstr : mreadstr;
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event = eccstr;
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} else {
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/* A CPU timeout or a DMA overrun. */
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cycle = (erraddr & KN0X_EAR_WRITE) ? writestr : readstr;
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event = (erraddr & KN0X_EAR_CPU) ? timestr : overstr;
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}
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address = erraddr & KN0X_EAR_ADDRESS;
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/* For ECC errors on reads adjust for MT pipelining. */
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if ((erraddr & (KN0X_EAR_WRITE | KN0X_EAR_ECCERR)) == KN0X_EAR_ECCERR)
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address = (address & ~0xfffLL) | ((address - 5) & 0xfffLL);
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address <<= 2;
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/* Only CPU errors are fixable. */
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if (erraddr & KN0X_EAR_CPU && is_fixup)
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action = MIPS_BE_FIXUP;
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if (erraddr & KN0X_EAR_ECCERR) {
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static const u8 data_sbit[32] = {
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0x4f, 0x4a, 0x52, 0x54, 0x57, 0x58, 0x5b, 0x5d,
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0x23, 0x25, 0x26, 0x29, 0x2a, 0x2c, 0x31, 0x34,
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0x0e, 0x0b, 0x13, 0x15, 0x16, 0x19, 0x1a, 0x1c,
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0x62, 0x64, 0x67, 0x68, 0x6b, 0x6d, 0x70, 0x75,
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};
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static const u8 data_mbit[25] = {
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0x07, 0x0d, 0x1f,
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0x2f, 0x32, 0x37, 0x38, 0x3b, 0x3d, 0x3e,
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0x43, 0x45, 0x46, 0x49, 0x4c, 0x51, 0x5e,
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0x61, 0x6e, 0x73, 0x76, 0x79, 0x7a, 0x7c, 0x7f,
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};
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static const char sbestr[] = "corrected single";
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static const char dbestr[] = "uncorrectable double";
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static const char mbestr[] = "uncorrectable multiple";
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if (!(address & 0x4))
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syn = chksyn; /* Low bank. */
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else
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syn = chksyn >> 16; /* High bank. */
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if (!(syn & KN0X_ESR_VLDLO)) {
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/* Ack now, no rewrite will happen. */
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dec_ecc_be_ack();
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fmt = KERN_ALERT "%s" "invalid\n";
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} else {
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sngl = syn & KN0X_ESR_SNGLO;
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syn &= KN0X_ESR_SYNLO;
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/*
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* Multibit errors may be tagged incorrectly;
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* check the syndrome explicitly.
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*/
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for (i = 0; i < 25; i++)
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if (syn == data_mbit[i])
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break;
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if (i < 25) {
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status = mbestr;
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} else if (!sngl) {
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status = dbestr;
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} else {
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volatile u32 *ptr =
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(void *)CKSEG1ADDR(address);
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*ptr = *ptr; /* Rewrite. */
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iob();
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status = sbestr;
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action = MIPS_BE_DISCARD;
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}
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/* Ack now, now we've rewritten (or not). */
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dec_ecc_be_ack();
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if (syn && syn == (syn & -syn)) {
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if (syn == 0x01) {
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fmt = KERN_ALERT "%s"
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"%#04x -- %s bit error "
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"at check bit C%s\n";
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xbit = "X";
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} else {
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fmt = KERN_ALERT "%s"
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"%#04x -- %s bit error "
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"at check bit C%s%u\n";
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}
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i = syn >> 2;
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} else {
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for (i = 0; i < 32; i++)
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if (syn == data_sbit[i])
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break;
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if (i < 32)
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fmt = KERN_ALERT "%s"
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"%#04x -- %s bit error "
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"at data bit D%s%u\n";
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else
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fmt = KERN_ALERT "%s"
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"%#04x -- %s bit error\n";
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}
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}
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}
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if (action != MIPS_BE_FIXUP)
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printk(KERN_ALERT "Bus error %s: %s %s %s at %#010lx\n",
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kind, agent, cycle, event, address);
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if (action != MIPS_BE_FIXUP && erraddr & KN0X_EAR_ECCERR)
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printk(fmt, " ECC syndrome ", syn, status, xbit, i);
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return action;
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}
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int dec_ecc_be_handler(struct pt_regs *regs, int is_fixup)
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{
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return dec_ecc_be_backend(regs, is_fixup, 0);
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}
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irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id)
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{
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struct pt_regs *regs = get_irq_regs();
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int action = dec_ecc_be_backend(regs, 0, 1);
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if (action == MIPS_BE_DISCARD)
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return IRQ_HANDLED;
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/*
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* FIXME: Find the affected processes and kill them, otherwise
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* we must die.
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*
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* The interrupt is asynchronously delivered thus EPC and RA
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* may be irrelevant, but are printed for a reference.
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*/
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printk(KERN_ALERT "Fatal bus interrupt, epc == %08lx, ra == %08lx\n",
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regs->cp0_epc, regs->regs[31]);
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die("Unrecoverable bus error", regs);
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}
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/*
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* Initialization differs a bit between KN02 and KN03/KN05, so we
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* need two variants. Once set up, all systems can be handled the
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* same way.
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*/
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static inline void dec_kn02_be_init(void)
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{
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volatile u32 *csr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR);
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kn0x_erraddr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_ERRADDR);
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kn0x_chksyn = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CHKSYN);
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/* Preset write-only bits of the Control Register cache. */
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cached_kn02_csr = *csr | KN02_CSR_LEDS;
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/* Set normal ECC detection and generation. */
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cached_kn02_csr &= ~(KN02_CSR_DIAGCHK | KN02_CSR_DIAGGEN);
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/* Enable ECC correction. */
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cached_kn02_csr |= KN02_CSR_CORRECT;
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*csr = cached_kn02_csr;
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iob();
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}
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static inline void dec_kn03_be_init(void)
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{
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volatile u32 *mcr = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_MCR);
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volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR);
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kn0x_erraddr = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_ERRADDR);
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kn0x_chksyn = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_CHKSYN);
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/*
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* Set normal ECC detection and generation, enable ECC correction.
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* For KN05 we also need to make sure EE (?) is enabled in the MB.
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* Otherwise DBE/IBE exceptions would be masked but bus error
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* interrupts would still arrive, resulting in an inevitable crash
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* if get_dbe() triggers one.
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*/
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*mcr = (*mcr & ~(KN03_MCR_DIAGCHK | KN03_MCR_DIAGGEN)) |
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KN03_MCR_CORRECT;
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if (current_cpu_type() == CPU_R4400SC)
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*mbcs |= KN4K_MB_CSR_EE;
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fast_iob();
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}
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void __init dec_ecc_be_init(void)
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{
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if (mips_machtype == MACH_DS5000_200)
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dec_kn02_be_init();
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else
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dec_kn03_be_init();
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/* Clear any leftover errors from the firmware. */
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dec_ecc_be_ack();
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}
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