ebaa81c728
The Samsung serial driver registered for CPU frequency transitions to recalculate its clock when ARM clock frequency changes. This is needed only on S3C24xx platform so limit the ifdef to respective cpufreq driver. On S3C24xx the ratio ratio between frequencies of UART's parent clock (pclk) and ARM's parent clock (fclk) remains fixed. Therefore when ARM clock frequency goes down, the serial is also affected. Suggested-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
155 lines
3.4 KiB
C
155 lines
3.4 KiB
C
#ifndef __SAMSUNG_H
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#define __SAMSUNG_H
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/*
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* Driver for Samsung SoC onboard UARTs.
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*
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* Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
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* http://armlinux.simtec.co.uk/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/dmaengine.h>
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struct s3c24xx_uart_info {
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char *name;
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unsigned int type;
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unsigned int fifosize;
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unsigned long rx_fifomask;
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unsigned long rx_fifoshift;
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unsigned long rx_fifofull;
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unsigned long tx_fifomask;
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unsigned long tx_fifoshift;
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unsigned long tx_fifofull;
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unsigned int def_clk_sel;
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unsigned long num_clks;
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unsigned long clksel_mask;
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unsigned long clksel_shift;
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/* uart port features */
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unsigned int has_divslot:1;
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/* uart controls */
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int (*reset_port)(struct uart_port *, struct s3c2410_uartcfg *);
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};
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struct s3c24xx_serial_drv_data {
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struct s3c24xx_uart_info *info;
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struct s3c2410_uartcfg *def_cfg;
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unsigned int fifosize[CONFIG_SERIAL_SAMSUNG_UARTS];
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};
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struct s3c24xx_uart_dma {
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dma_filter_fn fn;
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void *rx_param;
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void *tx_param;
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unsigned int rx_chan_id;
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unsigned int tx_chan_id;
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struct dma_slave_config rx_conf;
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struct dma_slave_config tx_conf;
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struct dma_chan *rx_chan;
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struct dma_chan *tx_chan;
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dma_addr_t rx_addr;
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dma_addr_t tx_addr;
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dma_cookie_t rx_cookie;
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dma_cookie_t tx_cookie;
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char *rx_buf;
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dma_addr_t tx_transfer_addr;
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size_t rx_size;
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size_t tx_size;
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struct dma_async_tx_descriptor *tx_desc;
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struct dma_async_tx_descriptor *rx_desc;
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int tx_bytes_requested;
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int rx_bytes_requested;
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};
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struct s3c24xx_uart_port {
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unsigned char rx_claimed;
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unsigned char tx_claimed;
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unsigned int pm_level;
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unsigned long baudclk_rate;
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unsigned int min_dma_size;
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unsigned int rx_irq;
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unsigned int tx_irq;
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unsigned int tx_in_progress;
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unsigned int tx_mode;
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unsigned int rx_mode;
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struct s3c24xx_uart_info *info;
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struct clk *clk;
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struct clk *baudclk;
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struct uart_port port;
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struct s3c24xx_serial_drv_data *drv_data;
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/* reference to platform data */
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struct s3c2410_uartcfg *cfg;
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struct s3c24xx_uart_dma *dma;
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#ifdef CONFIG_ARM_S3C24XX_CPUFREQ
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struct notifier_block freq_transition;
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#endif
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};
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/* conversion functions */
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#define s3c24xx_dev_to_port(__dev) dev_get_drvdata(__dev)
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/* register access controls */
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#define portaddr(port, reg) ((port)->membase + (reg))
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#define portaddrl(port, reg) \
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((unsigned long *)(unsigned long)((port)->membase + (reg)))
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#define rd_regb(port, reg) (readb_relaxed(portaddr(port, reg)))
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#define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg)))
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#define wr_regb(port, reg, val) writeb_relaxed(val, portaddr(port, reg))
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#define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg))
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/* Byte-order aware bit setting/clearing functions. */
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static inline void s3c24xx_set_bit(struct uart_port *port, int idx,
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unsigned int reg)
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{
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unsigned long flags;
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u32 val;
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local_irq_save(flags);
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val = rd_regl(port, reg);
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val |= (1 << idx);
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wr_regl(port, reg, val);
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local_irq_restore(flags);
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}
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static inline void s3c24xx_clear_bit(struct uart_port *port, int idx,
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unsigned int reg)
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{
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unsigned long flags;
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u32 val;
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local_irq_save(flags);
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val = rd_regl(port, reg);
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val &= ~(1 << idx);
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wr_regl(port, reg, val);
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local_irq_restore(flags);
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}
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#endif
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