7a0c819d28
Dave Jones reports that offlining a CPU leads to this trace: numa_remove_cpu cpu 1 node 0: mask now 0,2-3 smpboot: CPU 1 is now offline BUG: using smp_processor_id() in preemptible [00000000] code: cpu-offline.sh/10591 caller is cmci_rediscover+0x6a/0xe0 Pid: 10591, comm: cpu-offline.sh Not tainted 3.9.0-rc3+ #2 Call Trace: [<ffffffff81333bbd>] debug_smp_processor_id+0xdd/0x100 [<ffffffff8101edba>] cmci_rediscover+0x6a/0xe0 [<ffffffff815f5b9f>] mce_cpu_callback+0x19d/0x1ae [<ffffffff8160ea66>] notifier_call_chain+0x66/0x150 [<ffffffff8107ad7e>] __raw_notifier_call_chain+0xe/0x10 [<ffffffff8104c2e3>] cpu_notify+0x23/0x50 [<ffffffff8104c31e>] cpu_notify_nofail+0xe/0x20 [<ffffffff815ef082>] _cpu_down+0x302/0x350 [<ffffffff815ef106>] cpu_down+0x36/0x50 [<ffffffff815f1c9d>] store_online+0x8d/0xd0 [<ffffffff813edc48>] dev_attr_store+0x18/0x30 [<ffffffff81226eeb>] sysfs_write_file+0xdb/0x150 [<ffffffff811adfb2>] vfs_write+0xa2/0x170 [<ffffffff811ae16c>] sys_write+0x4c/0xa0 [<ffffffff81613019>] system_call_fastpath+0x16/0x1b However, a look at cmci_rediscover shows that it can be simplified quite a bit, apart from solving the above issue. It invokes functions that take spin locks with interrupts disabled, and hence it can run in atomic context. Also, it is run in the CPU_POST_DEAD phase, so the dying CPU is already dead and out of the cpu_online_mask. So take these points into account and simplify the code, and thereby also fix the above issue. Reported-by: Dave Jones <davej@redhat.com> Signed-off-by: Srivatsa S. Bhat <srivatsa.bhat@linux.vnet.ibm.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
232 lines
6.9 KiB
C
232 lines
6.9 KiB
C
#ifndef _ASM_X86_MCE_H
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#define _ASM_X86_MCE_H
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#include <uapi/asm/mce.h>
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/*
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* Machine Check support for x86
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*/
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/* MCG_CAP register defines */
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#define MCG_BANKCNT_MASK 0xff /* Number of Banks */
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#define MCG_CTL_P (1ULL<<8) /* MCG_CTL register available */
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#define MCG_EXT_P (1ULL<<9) /* Extended registers available */
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#define MCG_CMCI_P (1ULL<<10) /* CMCI supported */
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#define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */
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#define MCG_EXT_CNT_SHIFT 16
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#define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
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#define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */
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/* MCG_STATUS register defines */
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#define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
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#define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */
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#define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */
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/* MCi_STATUS register defines */
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#define MCI_STATUS_VAL (1ULL<<63) /* valid error */
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#define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */
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#define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */
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#define MCI_STATUS_EN (1ULL<<60) /* error enabled */
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#define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
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#define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
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#define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */
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#define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */
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#define MCI_STATUS_AR (1ULL<<55) /* Action required */
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#define MCACOD 0xffff /* MCA Error Code */
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/* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
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#define MCACOD_SCRUB 0x00C0 /* 0xC0-0xCF Memory Scrubbing */
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#define MCACOD_SCRUBMSK 0xfff0
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#define MCACOD_L3WB 0x017A /* L3 Explicit Writeback */
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#define MCACOD_DATA 0x0134 /* Data Load */
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#define MCACOD_INSTR 0x0150 /* Instruction Fetch */
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/* MCi_MISC register defines */
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#define MCI_MISC_ADDR_LSB(m) ((m) & 0x3f)
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#define MCI_MISC_ADDR_MODE(m) (((m) >> 6) & 7)
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#define MCI_MISC_ADDR_SEGOFF 0 /* segment offset */
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#define MCI_MISC_ADDR_LINEAR 1 /* linear address */
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#define MCI_MISC_ADDR_PHYS 2 /* physical address */
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#define MCI_MISC_ADDR_MEM 3 /* memory address */
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#define MCI_MISC_ADDR_GENERIC 7 /* generic */
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/* CTL2 register defines */
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#define MCI_CTL2_CMCI_EN (1ULL << 30)
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#define MCI_CTL2_CMCI_THRESHOLD_MASK 0x7fffULL
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#define MCJ_CTX_MASK 3
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#define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK)
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#define MCJ_CTX_RANDOM 0 /* inject context: random */
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#define MCJ_CTX_PROCESS 0x1 /* inject context: process */
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#define MCJ_CTX_IRQ 0x2 /* inject context: IRQ */
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#define MCJ_NMI_BROADCAST 0x4 /* do NMI broadcasting */
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#define MCJ_EXCEPTION 0x8 /* raise as exception */
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#define MCJ_IRQ_BRAODCAST 0x10 /* do IRQ broadcasting */
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#define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */
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/* Software defined banks */
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#define MCE_EXTENDED_BANK 128
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#define MCE_THERMAL_BANK (MCE_EXTENDED_BANK + 0)
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#define K8_MCE_THRESHOLD_BASE (MCE_EXTENDED_BANK + 1)
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#define MCE_LOG_LEN 32
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#define MCE_LOG_SIGNATURE "MACHINECHECK"
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/*
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* This structure contains all data related to the MCE log. Also
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* carries a signature to make it easier to find from external
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* debugging tools. Each entry is only valid when its finished flag
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* is set.
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*/
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struct mce_log {
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char signature[12]; /* "MACHINECHECK" */
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unsigned len; /* = MCE_LOG_LEN */
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unsigned next;
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unsigned flags;
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unsigned recordlen; /* length of struct mce */
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struct mce entry[MCE_LOG_LEN];
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};
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struct mca_config {
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bool dont_log_ce;
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bool cmci_disabled;
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bool ignore_ce;
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bool disabled;
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bool ser;
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bool bios_cmci_threshold;
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u8 banks;
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s8 bootlog;
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int tolerant;
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int monarch_timeout;
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int panic_timeout;
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u32 rip_msr;
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};
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extern struct mca_config mca_cfg;
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extern void mce_register_decode_chain(struct notifier_block *nb);
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extern void mce_unregister_decode_chain(struct notifier_block *nb);
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#include <linux/percpu.h>
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#include <linux/init.h>
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#include <linux/atomic.h>
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extern int mce_p5_enabled;
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#ifdef CONFIG_X86_MCE
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int mcheck_init(void);
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void mcheck_cpu_init(struct cpuinfo_x86 *c);
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#else
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static inline int mcheck_init(void) { return 0; }
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static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {}
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#endif
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#ifdef CONFIG_X86_ANCIENT_MCE
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void intel_p5_mcheck_init(struct cpuinfo_x86 *c);
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void winchip_mcheck_init(struct cpuinfo_x86 *c);
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static inline void enable_p5_mce(void) { mce_p5_enabled = 1; }
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#else
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static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {}
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static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {}
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static inline void enable_p5_mce(void) {}
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#endif
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void mce_setup(struct mce *m);
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void mce_log(struct mce *m);
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DECLARE_PER_CPU(struct device *, mce_device);
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/*
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* Maximum banks number.
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* This is the limit of the current register layout on
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* Intel CPUs.
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*/
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#define MAX_NR_BANKS 32
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#ifdef CONFIG_X86_MCE_INTEL
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void mce_intel_feature_init(struct cpuinfo_x86 *c);
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void cmci_clear(void);
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void cmci_reenable(void);
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void cmci_rediscover(void);
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void cmci_recheck(void);
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#else
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static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }
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static inline void cmci_clear(void) {}
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static inline void cmci_reenable(void) {}
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static inline void cmci_rediscover(void) {}
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static inline void cmci_recheck(void) {}
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#endif
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#ifdef CONFIG_X86_MCE_AMD
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void mce_amd_feature_init(struct cpuinfo_x86 *c);
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#else
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static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
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#endif
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int mce_available(struct cpuinfo_x86 *c);
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DECLARE_PER_CPU(unsigned, mce_exception_count);
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DECLARE_PER_CPU(unsigned, mce_poll_count);
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extern atomic_t mce_entry;
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typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS);
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DECLARE_PER_CPU(mce_banks_t, mce_poll_banks);
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enum mcp_flags {
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MCP_TIMESTAMP = (1 << 0), /* log time stamp */
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MCP_UC = (1 << 1), /* log uncorrected errors */
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MCP_DONTLOG = (1 << 2), /* only clear, don't log */
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};
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void machine_check_poll(enum mcp_flags flags, mce_banks_t *b);
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int mce_notify_irq(void);
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void mce_notify_process(void);
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DECLARE_PER_CPU(struct mce, injectm);
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extern void register_mce_write_callback(ssize_t (*)(struct file *filp,
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const char __user *ubuf,
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size_t usize, loff_t *off));
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/*
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* Exception handler
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*/
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/* Call the installed machine check handler for this CPU setup. */
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extern void (*machine_check_vector)(struct pt_regs *, long error_code);
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void do_machine_check(struct pt_regs *, long);
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/*
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* Threshold handler
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*/
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extern void (*mce_threshold_vector)(void);
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extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
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/*
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* Thermal handler
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*/
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void intel_init_thermal(struct cpuinfo_x86 *c);
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void mce_log_therm_throt_event(__u64 status);
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/* Interrupt Handler for core thermal thresholds */
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extern int (*platform_thermal_notify)(__u64 msr_val);
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#ifdef CONFIG_X86_THERMAL_VECTOR
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extern void mcheck_intel_therm_init(void);
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#else
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static inline void mcheck_intel_therm_init(void) { }
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#endif
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/*
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* Used by APEI to report memory error via /dev/mcelog
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*/
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struct cper_sec_mem_err;
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extern void apei_mce_report_mem_error(int corrected,
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struct cper_sec_mem_err *mem_err);
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#endif /* _ASM_X86_MCE_H */
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