89 lines
2.3 KiB
C
89 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Apex kernel-userspace interface definition(s).
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*
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* Copyright (C) 2018 Google, Inc.
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*/
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#ifndef __APEX_H__
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#define __APEX_H__
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#include <linux/ioctl.h>
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#include <linux/bitops.h>
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#include "gasket.h"
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/* Structural definitions/macros. */
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/* The number of PCI BARs. */
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#define APEX_NUM_BARS 3
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/* Size of a memory page in bytes, and the related number of bits to shift. */
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#define APEX_PAGE_SHIFT 12
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#define APEX_PAGE_SIZE BIT(APEX_PAGE_SHIFT)
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#define APEX_EXTENDED_SHIFT 63 /* Extended address bit position. */
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/*
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* Addresses are 2^3=8 bytes each. Page in second level page table holds
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* APEX_PAGE_SIZE/8 addresses.
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*/
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#define APEX_ADDR_SHIFT 3
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#define APEX_LEVEL_SHIFT (APEX_PAGE_SHIFT - APEX_ADDR_SHIFT)
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#define APEX_LEVEL_SIZE BIT(APEX_LEVEL_SHIFT)
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#define APEX_PAGE_TABLE_MAX 65536
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#define APEX_SIMPLE_PAGE_MAX APEX_PAGE_TABLE_MAX
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#define APEX_EXTENDED_PAGE_MAX (APEX_PAGE_TABLE_MAX << APEX_LEVEL_SHIFT)
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/* Check reset 120 times */
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#define APEX_RESET_RETRY 120
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/* Wait 100 ms between checks. Total 12 sec wait maximum. */
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#define APEX_RESET_DELAY 100
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#define APEX_CHIP_INIT_DONE 2
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#define APEX_RESET_ACCEPTED 0
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enum apex_reset_types {
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APEX_CHIP_REINIT_RESET = 3,
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};
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/* Interrupt defines */
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/* Gasket device interrupts enums must be dense (i.e., no empty slots). */
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enum apex_interrupt {
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APEX_INTERRUPT_INSTR_QUEUE = 0,
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APEX_INTERRUPT_INPUT_ACTV_QUEUE = 1,
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APEX_INTERRUPT_PARAM_QUEUE = 2,
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APEX_INTERRUPT_OUTPUT_ACTV_QUEUE = 3,
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APEX_INTERRUPT_SC_HOST_0 = 4,
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APEX_INTERRUPT_SC_HOST_1 = 5,
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APEX_INTERRUPT_SC_HOST_2 = 6,
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APEX_INTERRUPT_SC_HOST_3 = 7,
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APEX_INTERRUPT_TOP_LEVEL_0 = 8,
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APEX_INTERRUPT_TOP_LEVEL_1 = 9,
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APEX_INTERRUPT_TOP_LEVEL_2 = 10,
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APEX_INTERRUPT_TOP_LEVEL_3 = 11,
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APEX_INTERRUPT_FATAL_ERR = 12,
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APEX_INTERRUPT_COUNT = 13,
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};
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/*
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* Clock Gating ioctl.
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*/
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struct apex_gate_clock_ioctl {
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/* Enter or leave clock gated state. */
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u64 enable;
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/* If set, enter clock gating state, regardless of custom block's
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* internal idle state
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*/
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u64 force_idle;
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};
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/* Base number for all Apex-common IOCTLs */
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#define APEX_IOCTL_BASE 0x7F
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/* Enable/Disable clock gating. */
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#define APEX_IOCTL_GATE_CLOCK \
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_IOW(APEX_IOCTL_BASE, 0, struct apex_gate_clock_ioctl)
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#endif /* __APEX_H__ */
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