549 lines
14 KiB
C
549 lines
14 KiB
C
/*
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* Copyright (c) 2018, Mellanox Technologies. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include "port.h"
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/* speed in units of 1Mb */
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static const u32 mlx5e_link_speed[MLX5E_LINK_MODES_NUMBER] = {
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[MLX5E_1000BASE_CX_SGMII] = 1000,
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[MLX5E_1000BASE_KX] = 1000,
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[MLX5E_10GBASE_CX4] = 10000,
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[MLX5E_10GBASE_KX4] = 10000,
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[MLX5E_10GBASE_KR] = 10000,
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[MLX5E_20GBASE_KR2] = 20000,
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[MLX5E_40GBASE_CR4] = 40000,
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[MLX5E_40GBASE_KR4] = 40000,
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[MLX5E_56GBASE_R4] = 56000,
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[MLX5E_10GBASE_CR] = 10000,
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[MLX5E_10GBASE_SR] = 10000,
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[MLX5E_10GBASE_ER] = 10000,
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[MLX5E_40GBASE_SR4] = 40000,
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[MLX5E_40GBASE_LR4] = 40000,
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[MLX5E_50GBASE_SR2] = 50000,
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[MLX5E_100GBASE_CR4] = 100000,
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[MLX5E_100GBASE_SR4] = 100000,
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[MLX5E_100GBASE_KR4] = 100000,
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[MLX5E_100GBASE_LR4] = 100000,
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[MLX5E_100BASE_TX] = 100,
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[MLX5E_1000BASE_T] = 1000,
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[MLX5E_10GBASE_T] = 10000,
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[MLX5E_25GBASE_CR] = 25000,
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[MLX5E_25GBASE_KR] = 25000,
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[MLX5E_25GBASE_SR] = 25000,
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[MLX5E_50GBASE_CR2] = 50000,
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[MLX5E_50GBASE_KR2] = 50000,
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};
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static const u32 mlx5e_ext_link_speed[MLX5E_EXT_LINK_MODES_NUMBER] = {
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[MLX5E_SGMII_100M] = 100,
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[MLX5E_1000BASE_X_SGMII] = 1000,
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[MLX5E_5GBASE_R] = 5000,
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[MLX5E_10GBASE_XFI_XAUI_1] = 10000,
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[MLX5E_40GBASE_XLAUI_4_XLPPI_4] = 40000,
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[MLX5E_25GAUI_1_25GBASE_CR_KR] = 25000,
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[MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2] = 50000,
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[MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR] = 50000,
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[MLX5E_CAUI_4_100GBASE_CR4_KR4] = 100000,
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[MLX5E_100GAUI_2_100GBASE_CR2_KR2] = 100000,
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[MLX5E_200GAUI_4_200GBASE_CR4_KR4] = 200000,
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[MLX5E_400GAUI_8] = 400000,
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};
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static void mlx5e_port_get_speed_arr(struct mlx5_core_dev *mdev,
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const u32 **arr, u32 *size,
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bool force_legacy)
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{
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bool ext = force_legacy ? false : MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
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*size = ext ? ARRAY_SIZE(mlx5e_ext_link_speed) :
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ARRAY_SIZE(mlx5e_link_speed);
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*arr = ext ? mlx5e_ext_link_speed : mlx5e_link_speed;
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}
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int mlx5_port_query_eth_proto(struct mlx5_core_dev *dev, u8 port, bool ext,
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struct mlx5e_port_eth_proto *eproto)
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{
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u32 out[MLX5_ST_SZ_DW(ptys_reg)];
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int err;
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if (!eproto)
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return -EINVAL;
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err = mlx5_query_port_ptys(dev, out, sizeof(out), MLX5_PTYS_EN, port);
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if (err)
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return err;
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eproto->cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
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eth_proto_capability);
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eproto->admin = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_admin);
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eproto->oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper);
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return 0;
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}
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void mlx5_port_query_eth_autoneg(struct mlx5_core_dev *dev, u8 *an_status,
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u8 *an_disable_cap, u8 *an_disable_admin)
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{
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u32 out[MLX5_ST_SZ_DW(ptys_reg)];
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*an_status = 0;
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*an_disable_cap = 0;
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*an_disable_admin = 0;
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if (mlx5_query_port_ptys(dev, out, sizeof(out), MLX5_PTYS_EN, 1))
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return;
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*an_status = MLX5_GET(ptys_reg, out, an_status);
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*an_disable_cap = MLX5_GET(ptys_reg, out, an_disable_cap);
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*an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin);
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}
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int mlx5_port_set_eth_ptys(struct mlx5_core_dev *dev, bool an_disable,
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u32 proto_admin, bool ext)
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{
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u32 out[MLX5_ST_SZ_DW(ptys_reg)];
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u32 in[MLX5_ST_SZ_DW(ptys_reg)];
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u8 an_disable_admin;
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u8 an_disable_cap;
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u8 an_status;
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mlx5_port_query_eth_autoneg(dev, &an_status, &an_disable_cap,
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&an_disable_admin);
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if (!an_disable_cap && an_disable)
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return -EPERM;
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memset(in, 0, sizeof(in));
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MLX5_SET(ptys_reg, in, local_port, 1);
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MLX5_SET(ptys_reg, in, an_disable_admin, an_disable);
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MLX5_SET(ptys_reg, in, proto_mask, MLX5_PTYS_EN);
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if (ext)
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MLX5_SET(ptys_reg, in, ext_eth_proto_admin, proto_admin);
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else
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MLX5_SET(ptys_reg, in, eth_proto_admin, proto_admin);
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return mlx5_core_access_reg(dev, in, sizeof(in), out,
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sizeof(out), MLX5_REG_PTYS, 0, 1);
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}
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u32 mlx5e_port_ptys2speed(struct mlx5_core_dev *mdev, u32 eth_proto_oper,
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bool force_legacy)
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{
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unsigned long temp = eth_proto_oper;
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const u32 *table;
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u32 speed = 0;
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u32 max_size;
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int i;
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mlx5e_port_get_speed_arr(mdev, &table, &max_size, force_legacy);
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i = find_first_bit(&temp, max_size);
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if (i < max_size)
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speed = table[i];
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return speed;
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}
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int mlx5e_port_linkspeed(struct mlx5_core_dev *mdev, u32 *speed)
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{
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struct mlx5e_port_eth_proto eproto;
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bool force_legacy = false;
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bool ext;
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int err;
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ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
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err = mlx5_port_query_eth_proto(mdev, 1, ext, &eproto);
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if (err)
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goto out;
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if (ext && !eproto.admin) {
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force_legacy = true;
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err = mlx5_port_query_eth_proto(mdev, 1, false, &eproto);
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if (err)
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goto out;
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}
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*speed = mlx5e_port_ptys2speed(mdev, eproto.oper, force_legacy);
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if (!(*speed))
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err = -EINVAL;
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out:
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return err;
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}
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int mlx5e_port_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed)
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{
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struct mlx5e_port_eth_proto eproto;
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u32 max_speed = 0;
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const u32 *table;
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u32 max_size;
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bool ext;
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int err;
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int i;
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ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
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err = mlx5_port_query_eth_proto(mdev, 1, ext, &eproto);
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if (err)
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return err;
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mlx5e_port_get_speed_arr(mdev, &table, &max_size, false);
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for (i = 0; i < max_size; ++i)
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if (eproto.cap & MLX5E_PROT_MASK(i))
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max_speed = max(max_speed, table[i]);
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*speed = max_speed;
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return 0;
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}
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u32 mlx5e_port_speed2linkmodes(struct mlx5_core_dev *mdev, u32 speed,
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bool force_legacy)
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{
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u32 link_modes = 0;
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const u32 *table;
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u32 max_size;
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int i;
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mlx5e_port_get_speed_arr(mdev, &table, &max_size, force_legacy);
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for (i = 0; i < max_size; ++i) {
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if (table[i] == speed)
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link_modes |= MLX5E_PROT_MASK(i);
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}
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return link_modes;
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}
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int mlx5e_port_query_pbmc(struct mlx5_core_dev *mdev, void *out)
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{
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int sz = MLX5_ST_SZ_BYTES(pbmc_reg);
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void *in;
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int err;
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in = kzalloc(sz, GFP_KERNEL);
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if (!in)
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return -ENOMEM;
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MLX5_SET(pbmc_reg, in, local_port, 1);
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err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PBMC, 0, 0);
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kfree(in);
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return err;
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}
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int mlx5e_port_set_pbmc(struct mlx5_core_dev *mdev, void *in)
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{
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int sz = MLX5_ST_SZ_BYTES(pbmc_reg);
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void *out;
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int err;
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out = kzalloc(sz, GFP_KERNEL);
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if (!out)
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return -ENOMEM;
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MLX5_SET(pbmc_reg, in, local_port, 1);
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err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PBMC, 0, 1);
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kfree(out);
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return err;
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}
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/* buffer[i]: buffer that priority i mapped to */
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int mlx5e_port_query_priority2buffer(struct mlx5_core_dev *mdev, u8 *buffer)
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{
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int sz = MLX5_ST_SZ_BYTES(pptb_reg);
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u32 prio_x_buff;
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void *out;
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void *in;
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int prio;
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int err;
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in = kzalloc(sz, GFP_KERNEL);
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out = kzalloc(sz, GFP_KERNEL);
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if (!in || !out) {
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err = -ENOMEM;
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goto out;
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}
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MLX5_SET(pptb_reg, in, local_port, 1);
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err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPTB, 0, 0);
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if (err)
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goto out;
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prio_x_buff = MLX5_GET(pptb_reg, out, prio_x_buff);
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for (prio = 0; prio < 8; prio++) {
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buffer[prio] = (u8)(prio_x_buff >> (4 * prio)) & 0xF;
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mlx5_core_dbg(mdev, "prio %d, buffer %d\n", prio, buffer[prio]);
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}
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out:
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kfree(in);
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kfree(out);
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return err;
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}
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int mlx5e_port_set_priority2buffer(struct mlx5_core_dev *mdev, u8 *buffer)
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{
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int sz = MLX5_ST_SZ_BYTES(pptb_reg);
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u32 prio_x_buff;
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void *out;
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void *in;
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int prio;
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int err;
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in = kzalloc(sz, GFP_KERNEL);
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out = kzalloc(sz, GFP_KERNEL);
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if (!in || !out) {
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err = -ENOMEM;
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goto out;
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}
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/* First query the pptb register */
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MLX5_SET(pptb_reg, in, local_port, 1);
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err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPTB, 0, 0);
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if (err)
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goto out;
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memcpy(in, out, sz);
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MLX5_SET(pptb_reg, in, local_port, 1);
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/* Update the pm and prio_x_buff */
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MLX5_SET(pptb_reg, in, pm, 0xFF);
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prio_x_buff = 0;
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for (prio = 0; prio < 8; prio++)
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prio_x_buff |= (buffer[prio] << (4 * prio));
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MLX5_SET(pptb_reg, in, prio_x_buff, prio_x_buff);
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err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPTB, 0, 1);
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out:
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kfree(in);
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kfree(out);
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return err;
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}
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static u32 fec_supported_speeds[] = {
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10000,
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40000,
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25000,
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50000,
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56000,
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100000
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};
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#define MLX5E_FEC_SUPPORTED_SPEEDS ARRAY_SIZE(fec_supported_speeds)
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/* get/set FEC admin field for a given speed */
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static int mlx5e_fec_admin_field(u32 *pplm,
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u8 *fec_policy,
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bool write,
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u32 speed)
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{
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switch (speed) {
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case 10000:
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case 40000:
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if (!write)
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*fec_policy = MLX5_GET(pplm_reg, pplm,
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fec_override_admin_10g_40g);
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else
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MLX5_SET(pplm_reg, pplm,
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fec_override_admin_10g_40g, *fec_policy);
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break;
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case 25000:
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if (!write)
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*fec_policy = MLX5_GET(pplm_reg, pplm,
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fec_override_admin_25g);
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else
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MLX5_SET(pplm_reg, pplm,
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fec_override_admin_25g, *fec_policy);
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break;
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case 50000:
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if (!write)
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*fec_policy = MLX5_GET(pplm_reg, pplm,
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fec_override_admin_50g);
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else
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MLX5_SET(pplm_reg, pplm,
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fec_override_admin_50g, *fec_policy);
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break;
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case 56000:
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if (!write)
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*fec_policy = MLX5_GET(pplm_reg, pplm,
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fec_override_admin_56g);
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else
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MLX5_SET(pplm_reg, pplm,
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fec_override_admin_56g, *fec_policy);
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break;
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case 100000:
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if (!write)
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*fec_policy = MLX5_GET(pplm_reg, pplm,
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fec_override_admin_100g);
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else
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MLX5_SET(pplm_reg, pplm,
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fec_override_admin_100g, *fec_policy);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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/* returns FEC capabilities for a given speed */
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static int mlx5e_get_fec_cap_field(u32 *pplm,
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u8 *fec_cap,
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u32 speed)
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{
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switch (speed) {
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case 10000:
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case 40000:
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*fec_cap = MLX5_GET(pplm_reg, pplm,
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fec_override_cap_10g_40g);
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break;
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case 25000:
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*fec_cap = MLX5_GET(pplm_reg, pplm,
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fec_override_cap_25g);
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break;
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case 50000:
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*fec_cap = MLX5_GET(pplm_reg, pplm,
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fec_override_cap_50g);
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break;
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case 56000:
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*fec_cap = MLX5_GET(pplm_reg, pplm,
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fec_override_cap_56g);
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break;
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case 100000:
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*fec_cap = MLX5_GET(pplm_reg, pplm,
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fec_override_cap_100g);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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int mlx5e_get_fec_caps(struct mlx5_core_dev *dev, u8 *fec_caps)
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{
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u32 out[MLX5_ST_SZ_DW(pplm_reg)] = {};
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u32 in[MLX5_ST_SZ_DW(pplm_reg)] = {};
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int sz = MLX5_ST_SZ_BYTES(pplm_reg);
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u32 current_fec_speed;
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int err;
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if (!MLX5_CAP_GEN(dev, pcam_reg))
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return -EOPNOTSUPP;
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if (!MLX5_CAP_PCAM_REG(dev, pplm))
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return -EOPNOTSUPP;
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MLX5_SET(pplm_reg, in, local_port, 1);
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err = mlx5_core_access_reg(dev, in, sz, out, sz, MLX5_REG_PPLM, 0, 0);
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if (err)
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return err;
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err = mlx5e_port_linkspeed(dev, ¤t_fec_speed);
|
|
if (err)
|
|
return err;
|
|
|
|
return mlx5e_get_fec_cap_field(out, fec_caps, current_fec_speed);
|
|
}
|
|
|
|
int mlx5e_get_fec_mode(struct mlx5_core_dev *dev, u32 *fec_mode_active,
|
|
u8 *fec_configured_mode)
|
|
{
|
|
u32 out[MLX5_ST_SZ_DW(pplm_reg)] = {};
|
|
u32 in[MLX5_ST_SZ_DW(pplm_reg)] = {};
|
|
int sz = MLX5_ST_SZ_BYTES(pplm_reg);
|
|
u32 link_speed;
|
|
int err;
|
|
|
|
if (!MLX5_CAP_GEN(dev, pcam_reg))
|
|
return -EOPNOTSUPP;
|
|
|
|
if (!MLX5_CAP_PCAM_REG(dev, pplm))
|
|
return -EOPNOTSUPP;
|
|
|
|
MLX5_SET(pplm_reg, in, local_port, 1);
|
|
err = mlx5_core_access_reg(dev, in, sz, out, sz, MLX5_REG_PPLM, 0, 0);
|
|
if (err)
|
|
return err;
|
|
|
|
*fec_mode_active = MLX5_GET(pplm_reg, out, fec_mode_active);
|
|
|
|
if (!fec_configured_mode)
|
|
return 0;
|
|
|
|
err = mlx5e_port_linkspeed(dev, &link_speed);
|
|
if (err)
|
|
return err;
|
|
|
|
return mlx5e_fec_admin_field(out, fec_configured_mode, 0, link_speed);
|
|
}
|
|
|
|
int mlx5e_set_fec_mode(struct mlx5_core_dev *dev, u8 fec_policy)
|
|
{
|
|
u8 fec_policy_nofec = BIT(MLX5E_FEC_NOFEC);
|
|
bool fec_mode_not_supp_in_speed = false;
|
|
u32 out[MLX5_ST_SZ_DW(pplm_reg)] = {};
|
|
u32 in[MLX5_ST_SZ_DW(pplm_reg)] = {};
|
|
int sz = MLX5_ST_SZ_BYTES(pplm_reg);
|
|
u8 fec_policy_auto = 0;
|
|
u8 fec_caps = 0;
|
|
int err;
|
|
int i;
|
|
|
|
if (!MLX5_CAP_GEN(dev, pcam_reg))
|
|
return -EOPNOTSUPP;
|
|
|
|
if (!MLX5_CAP_PCAM_REG(dev, pplm))
|
|
return -EOPNOTSUPP;
|
|
|
|
MLX5_SET(pplm_reg, in, local_port, 1);
|
|
err = mlx5_core_access_reg(dev, in, sz, out, sz, MLX5_REG_PPLM, 0, 0);
|
|
if (err)
|
|
return err;
|
|
|
|
MLX5_SET(pplm_reg, out, local_port, 1);
|
|
|
|
for (i = 0; i < MLX5E_FEC_SUPPORTED_SPEEDS; i++) {
|
|
mlx5e_get_fec_cap_field(out, &fec_caps, fec_supported_speeds[i]);
|
|
/* policy supported for link speed, or policy is auto */
|
|
if (fec_caps & fec_policy || fec_policy == fec_policy_auto) {
|
|
mlx5e_fec_admin_field(out, &fec_policy, 1,
|
|
fec_supported_speeds[i]);
|
|
} else {
|
|
/* turn off FEC if supported. Else, leave it the same */
|
|
if (fec_caps & fec_policy_nofec)
|
|
mlx5e_fec_admin_field(out, &fec_policy_nofec, 1,
|
|
fec_supported_speeds[i]);
|
|
fec_mode_not_supp_in_speed = true;
|
|
}
|
|
}
|
|
|
|
if (fec_mode_not_supp_in_speed)
|
|
mlx5_core_dbg(dev,
|
|
"FEC policy 0x%x is not supported for some speeds",
|
|
fec_policy);
|
|
|
|
return mlx5_core_access_reg(dev, out, sz, out, sz, MLX5_REG_PPLM, 0, 1);
|
|
}
|