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alistair23-linux/arch/csky/include
Guo Ren 96354ad79e csky: fixup CACHEV1 store instruction fast retire
For I/O access, 810/807 store instruction fast retire will cause wrong
primitive. For example:

	stw (clear interrupt source)
	stw (unmask interrupt controller)
	enable interrupt

stw is fast retire instruction. When PC is run at enable interrupt
stage, the clear interrupt source hasn't finished. It will cause another
wrong irq-enter.

So use mb() to prevent above.

Signed-off-by: Guo Ren <ren_guo@c-sky.com>
Cc: Lu Baoquan <lu.baoquan@intellif.com>
2019-01-08 23:42:42 +08:00
..
asm csky: fixup CACHEV1 store instruction fast retire 2019-01-08 23:42:42 +08:00
uapi/asm arch: remove redundant UAPI generic-y defines 2019-01-06 10:22:15 +09:00