121 lines
3.7 KiB
C
121 lines
3.7 KiB
C
/*
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* VGICv2 MMIO handling functions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/irqchip/arm-gic.h>
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#include <linux/kvm.h>
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#include <linux/kvm_host.h>
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#include <kvm/iodev.h>
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#include <kvm/arm_vgic.h>
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#include "vgic.h"
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#include "vgic-mmio.h"
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static unsigned long vgic_mmio_read_v2_misc(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len)
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{
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u32 value;
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switch (addr & 0x0c) {
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case GIC_DIST_CTRL:
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value = vcpu->kvm->arch.vgic.enabled ? GICD_ENABLE : 0;
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break;
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case GIC_DIST_CTR:
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value = vcpu->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
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value = (value >> 5) - 1;
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value |= (atomic_read(&vcpu->kvm->online_vcpus) - 1) << 5;
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break;
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case GIC_DIST_IIDR:
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value = (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
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break;
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default:
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return 0;
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}
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return value;
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}
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static void vgic_mmio_write_v2_misc(struct kvm_vcpu *vcpu,
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gpa_t addr, unsigned int len,
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unsigned long val)
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{
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struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
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bool was_enabled = dist->enabled;
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switch (addr & 0x0c) {
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case GIC_DIST_CTRL:
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dist->enabled = val & GICD_ENABLE;
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if (!was_enabled && dist->enabled)
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vgic_kick_vcpus(vcpu->kvm);
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break;
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case GIC_DIST_CTR:
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case GIC_DIST_IIDR:
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/* Nothing to do */
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return;
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}
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}
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static const struct vgic_register_region vgic_v2_dist_registers[] = {
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REGISTER_DESC_WITH_LENGTH(GIC_DIST_CTRL,
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vgic_mmio_read_v2_misc, vgic_mmio_write_v2_misc, 12,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_IGROUP,
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vgic_mmio_read_rao, vgic_mmio_write_wi, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ENABLE_SET,
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vgic_mmio_read_enable, vgic_mmio_write_senable, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ENABLE_CLEAR,
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vgic_mmio_read_enable, vgic_mmio_write_cenable, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PENDING_SET,
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vgic_mmio_read_pending, vgic_mmio_write_spending, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PENDING_CLEAR,
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vgic_mmio_read_pending, vgic_mmio_write_cpending, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ACTIVE_SET,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ACTIVE_CLEAR,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 1,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PRI,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
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VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_TARGET,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
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VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
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REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_CONFIG,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 2,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GIC_DIST_SOFTINT,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
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VGIC_ACCESS_32bit),
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REGISTER_DESC_WITH_LENGTH(GIC_DIST_SGI_PENDING_CLEAR,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 16,
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VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
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REGISTER_DESC_WITH_LENGTH(GIC_DIST_SGI_PENDING_SET,
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vgic_mmio_read_raz, vgic_mmio_write_wi, 16,
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VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
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};
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unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev)
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{
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dev->regions = vgic_v2_dist_registers;
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dev->nr_regions = ARRAY_SIZE(vgic_v2_dist_registers);
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kvm_iodevice_init(&dev->dev, &kvm_io_gic_ops);
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return SZ_4K;
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}
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