ba5a37e521
Move the kirkwood DT support into mach-mvebu, and make them part of ARCH_MULTI_V5. Minimal changes have been made in order to make it boot. Cleanup of the header files and integration with mvebu will take place in following patches. In order to help Debian transition between mach-kirkwood and mach-mvebu, the DTS files are compiled for both, allowing Debian to continue using mach-kirkwood until all remaining boards are supported by mach-mvebu. Debian is then expected to simply swap from mach-kirkwood to mach-mvebu and mach-kirkwood will be removed. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Arnd Bergmann <arnd@arndb.de> Tested-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
143 lines
4.8 KiB
C
143 lines
4.8 KiB
C
/*
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* arch/arm/mach-mvebu/include/mach/kirkwood.h
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*
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* Generic definitions for Marvell Kirkwood SoC flavors:
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* 88F6180, 88F6192 and 88F6281.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARCH_KIRKWOOD_H
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#define __ASM_ARCH_KIRKWOOD_H
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/*
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* Marvell Kirkwood address maps.
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*
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* phys
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* e0000000 PCIe #0 Memory space
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* e8000000 PCIe #1 Memory space
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* f1000000 on-chip peripheral registers
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* f2000000 PCIe #0 I/O space
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* f3000000 PCIe #1 I/O space
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* f4000000 NAND controller address window
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* f5000000 Security Accelerator SRAM
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*
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* virt phys size
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* fed00000 f1000000 1M on-chip peripheral registers
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* fee00000 f2000000 1M PCIe #0 I/O space
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* fef00000 f3000000 1M PCIe #1 I/O space
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*/
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#define KIRKWOOD_SRAM_PHYS_BASE 0xf5000000
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#define KIRKWOOD_SRAM_SIZE SZ_2K
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#define KIRKWOOD_NAND_MEM_PHYS_BASE 0xf4000000
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#define KIRKWOOD_NAND_MEM_SIZE SZ_1K
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#define KIRKWOOD_PCIE1_IO_PHYS_BASE 0xf3000000
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#define KIRKWOOD_PCIE1_IO_BUS_BASE 0x00010000
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#define KIRKWOOD_PCIE1_IO_SIZE SZ_64K
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#define KIRKWOOD_PCIE_IO_PHYS_BASE 0xf2000000
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#define KIRKWOOD_PCIE_IO_BUS_BASE 0x00000000
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#define KIRKWOOD_PCIE_IO_SIZE SZ_64K
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#define KIRKWOOD_REGS_PHYS_BASE 0xf1000000
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#define KIRKWOOD_REGS_VIRT_BASE IOMEM(0xfed00000)
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#define KIRKWOOD_REGS_SIZE SZ_1M
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#define KIRKWOOD_PCIE_MEM_PHYS_BASE 0xe0000000
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#define KIRKWOOD_PCIE_MEM_BUS_BASE 0xe0000000
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#define KIRKWOOD_PCIE_MEM_SIZE SZ_128M
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#define KIRKWOOD_PCIE1_MEM_PHYS_BASE 0xe8000000
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#define KIRKWOOD_PCIE1_MEM_BUS_BASE 0xe8000000
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#define KIRKWOOD_PCIE1_MEM_SIZE SZ_128M
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/*
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* Register Map
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*/
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#define DDR_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x00000)
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#define DDR_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x00000)
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#define DDR_WINDOW_CPU_BASE (DDR_PHYS_BASE + 0x1500)
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#define DDR_WINDOW_CPU_SZ (0x20)
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#define DDR_OPERATION_BASE (DDR_PHYS_BASE + 0x1418)
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#define DEV_BUS_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x10000)
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#define DEV_BUS_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x10000)
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#define SAMPLE_AT_RESET (DEV_BUS_VIRT_BASE + 0x0030)
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#define DEVICE_ID (DEV_BUS_VIRT_BASE + 0x0034)
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#define GPIO_LOW_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x0100)
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#define GPIO_HIGH_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x0140)
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#define RTC_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x0300)
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#define SPI_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x0600)
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#define I2C_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1000)
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#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2000)
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#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2000)
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#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2100)
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#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2100)
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#define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x20000)
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#define BRIDGE_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x20000)
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#define BRIDGE_WINS_BASE (BRIDGE_PHYS_BASE)
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#define BRIDGE_WINS_SZ (0x80)
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#define CRYPTO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x30000)
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#define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x40000)
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#define PCIE_LINK_CTRL (PCIE_VIRT_BASE + 0x70)
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#define PCIE_STATUS (PCIE_VIRT_BASE + 0x1a04)
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#define PCIE1_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x44000)
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#define PCIE1_LINK_CTRL (PCIE1_VIRT_BASE + 0x70)
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#define PCIE1_STATUS (PCIE1_VIRT_BASE + 0x1a04)
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#define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x50000)
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#define XOR0_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x60800)
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#define XOR0_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x60800)
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#define XOR1_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x60900)
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#define XOR1_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x60900)
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#define XOR0_HIGH_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x60A00)
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#define XOR0_HIGH_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x60A00)
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#define XOR1_HIGH_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x60B00)
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#define XOR1_HIGH_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x60B00)
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#define GE00_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x70000)
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#define GE01_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x74000)
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#define SATA_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x80000)
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#define SATA_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x80000)
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#define SATA0_IF_CTRL (SATA_VIRT_BASE + 0x2050)
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#define SATA0_PHY_MODE_2 (SATA_VIRT_BASE + 0x2330)
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#define SATA1_IF_CTRL (SATA_VIRT_BASE + 0x4050)
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#define SATA1_PHY_MODE_2 (SATA_VIRT_BASE + 0x4330)
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#define SDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x90000)
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#define AUDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0xA0000)
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#define AUDIO_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0xA0000)
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/*
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* Supported devices and revisions.
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*/
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#define MV88F6281_DEV_ID 0x6281
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#define MV88F6281_REV_Z0 0
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#define MV88F6281_REV_A0 2
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#define MV88F6281_REV_A1 3
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#define MV88F6192_DEV_ID 0x6192
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#define MV88F6192_REV_Z0 0
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#define MV88F6192_REV_A0 2
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#define MV88F6192_REV_A1 3
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#define MV88F6180_DEV_ID 0x6180
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#define MV88F6180_REV_A0 2
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#define MV88F6180_REV_A1 3
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#define MV88F6282_DEV_ID 0x6282
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#define MV88F6282_REV_A0 0
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#define MV88F6282_REV_A1 1
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#endif
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