6efc3fe0f4
Commit c1d1cd597f ("ARM: OMAP2+:
omap_device: remove obsolete pm_lats and early_device code") missed a
few omap_device_build() calls that aren't included as part of the default
OMAP2+ Kconfig, omap2plus_defconfig.
Ideally, all devices that are present on the SoC should be created by
default, and only the corresponding device driver should be configured
or deconfigured in Kconfig. This allows drivers to be built as
modules and loaded later, even if they weren't part of the original
kernel build. Unfortunately, we're not quite there yet.
Thanks to Tony Lindgren for reporting this, found during his
randconfig tests.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
116 lines
3.2 KiB
C
116 lines
3.2 KiB
C
/*
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* Copyright (C) 2011 Ilya Yanok, Emcraft Systems
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*
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* Based on mach-omap2/board-am3517evm.c
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* Copyright (C) 2009 Texas Instruments Incorporated
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* Author: Ranjith Lohithakshan <ranjithl@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2
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* published by the Free Software Foundation.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
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* whether express or implied; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*/
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#include <linux/err.h>
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#include <linux/davinci_emac.h>
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#include <asm/system.h>
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#include "omap_device.h"
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#include "am35xx.h"
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#include "control.h"
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#include "am35xx-emac.h"
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static void am35xx_enable_emac_int(void)
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{
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u32 v;
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v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
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v |= (AM35XX_CPGMAC_C0_RX_PULSE_CLR | AM35XX_CPGMAC_C0_TX_PULSE_CLR |
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AM35XX_CPGMAC_C0_MISC_PULSE_CLR | AM35XX_CPGMAC_C0_RX_THRESH_CLR);
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omap_ctrl_writel(v, AM35XX_CONTROL_LVL_INTR_CLEAR);
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omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); /* OCP barrier */
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}
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static void am35xx_disable_emac_int(void)
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{
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u32 v;
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v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
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v |= (AM35XX_CPGMAC_C0_RX_PULSE_CLR | AM35XX_CPGMAC_C0_TX_PULSE_CLR);
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omap_ctrl_writel(v, AM35XX_CONTROL_LVL_INTR_CLEAR);
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omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); /* OCP barrier */
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}
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static struct emac_platform_data am35xx_emac_pdata = {
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.ctrl_reg_offset = AM35XX_EMAC_CNTRL_OFFSET,
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.ctrl_mod_reg_offset = AM35XX_EMAC_CNTRL_MOD_OFFSET,
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.ctrl_ram_offset = AM35XX_EMAC_CNTRL_RAM_OFFSET,
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.ctrl_ram_size = AM35XX_EMAC_CNTRL_RAM_SIZE,
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.hw_ram_addr = AM35XX_EMAC_HW_RAM_ADDR,
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.version = EMAC_VERSION_2,
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.interrupt_enable = am35xx_enable_emac_int,
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.interrupt_disable = am35xx_disable_emac_int,
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};
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static struct mdio_platform_data am35xx_mdio_pdata;
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static int __init omap_davinci_emac_dev_init(struct omap_hwmod *oh,
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void *pdata, int pdata_len)
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{
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struct platform_device *pdev;
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pdev = omap_device_build(oh->class->name, 0, oh, pdata, pdata_len);
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if (IS_ERR(pdev)) {
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WARN(1, "Can't build omap_device for %s:%s.\n",
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oh->class->name, oh->name);
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return PTR_ERR(pdev);
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}
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return 0;
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}
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void __init am35xx_emac_init(unsigned long mdio_bus_freq, u8 rmii_en)
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{
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struct omap_hwmod *oh;
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u32 v;
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int ret;
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oh = omap_hwmod_lookup("davinci_mdio");
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if (!oh) {
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pr_err("Could not find davinci_mdio hwmod\n");
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return;
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}
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am35xx_mdio_pdata.bus_freq = mdio_bus_freq;
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ret = omap_davinci_emac_dev_init(oh, &am35xx_mdio_pdata,
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sizeof(am35xx_mdio_pdata));
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if (ret) {
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pr_err("Could not build davinci_mdio hwmod device\n");
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return;
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}
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oh = omap_hwmod_lookup("davinci_emac");
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if (!oh) {
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pr_err("Could not find davinci_emac hwmod\n");
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return;
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}
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am35xx_emac_pdata.rmii_en = rmii_en;
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ret = omap_davinci_emac_dev_init(oh, &am35xx_emac_pdata,
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sizeof(am35xx_emac_pdata));
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if (ret) {
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pr_err("Could not build davinci_emac hwmod device\n");
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return;
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}
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v = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
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v &= ~AM35XX_CPGMACSS_SW_RST;
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omap_ctrl_writel(v, AM35XX_CONTROL_IP_SW_RESET);
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omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); /* OCP barrier */
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}
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