135 lines
3.9 KiB
C
135 lines
3.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DPU_CORE_PERF_H_
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#define _DPU_CORE_PERF_H_
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#include <linux/types.h>
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#include <linux/dcache.h>
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#include <linux/mutex.h>
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#include <drm/drm_crtc.h>
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#include "dpu_hw_catalog.h"
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#define DPU_PERF_DEFAULT_MAX_CORE_CLK_RATE 412500000
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/**
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* enum dpu_core_perf_data_bus_id - data bus identifier
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* @DPU_CORE_PERF_DATA_BUS_ID_MNOC: DPU/MNOC data bus
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* @DPU_CORE_PERF_DATA_BUS_ID_LLCC: MNOC/LLCC data bus
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* @DPU_CORE_PERF_DATA_BUS_ID_EBI: LLCC/EBI data bus
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*/
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enum dpu_core_perf_data_bus_id {
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DPU_CORE_PERF_DATA_BUS_ID_MNOC,
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DPU_CORE_PERF_DATA_BUS_ID_LLCC,
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DPU_CORE_PERF_DATA_BUS_ID_EBI,
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DPU_CORE_PERF_DATA_BUS_ID_MAX,
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};
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/**
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* struct dpu_core_perf_params - definition of performance parameters
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* @max_per_pipe_ib: maximum instantaneous bandwidth request
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* @bw_ctl: arbitrated bandwidth request
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* @core_clk_rate: core clock rate request
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*/
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struct dpu_core_perf_params {
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u64 max_per_pipe_ib[DPU_CORE_PERF_DATA_BUS_ID_MAX];
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u64 bw_ctl[DPU_CORE_PERF_DATA_BUS_ID_MAX];
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u64 core_clk_rate;
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};
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/**
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* struct dpu_core_perf_tune - definition of performance tuning control
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* @mode: performance mode
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* @min_core_clk: minimum core clock
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* @min_bus_vote: minimum bus vote
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*/
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struct dpu_core_perf_tune {
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u32 mode;
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u64 min_core_clk;
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u64 min_bus_vote;
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};
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/**
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* struct dpu_core_perf - definition of core performance context
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* @dev: Pointer to drm device
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* @debugfs_root: top level debug folder
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* @catalog: Pointer to catalog configuration
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* @core_clk: Pointer to core clock structure
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* @core_clk_rate: current core clock rate
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* @max_core_clk_rate: maximum allowable core clock rate
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* @perf_tune: debug control for performance tuning
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* @enable_bw_release: debug control for bandwidth release
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* @fix_core_clk_rate: fixed core clock request in Hz used in mode 2
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* @fix_core_ib_vote: fixed core ib vote in bps used in mode 2
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* @fix_core_ab_vote: fixed core ab vote in bps used in mode 2
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*/
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struct dpu_core_perf {
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struct drm_device *dev;
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struct dentry *debugfs_root;
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struct dpu_mdss_cfg *catalog;
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struct dss_clk *core_clk;
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u64 core_clk_rate;
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u64 max_core_clk_rate;
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struct dpu_core_perf_tune perf_tune;
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u32 enable_bw_release;
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u64 fix_core_clk_rate;
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u64 fix_core_ib_vote;
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u64 fix_core_ab_vote;
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};
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/**
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* dpu_core_perf_crtc_check - validate performance of the given crtc state
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* @crtc: Pointer to crtc
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* @state: Pointer to new crtc state
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* return: zero if success, or error code otherwise
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*/
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int dpu_core_perf_crtc_check(struct drm_crtc *crtc,
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struct drm_crtc_state *state);
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/**
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* dpu_core_perf_crtc_update - update performance of the given crtc
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* @crtc: Pointer to crtc
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* @params_changed: true if crtc parameters are modified
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* @stop_req: true if this is a stop request
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* return: zero if success, or error code otherwise
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*/
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int dpu_core_perf_crtc_update(struct drm_crtc *crtc,
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int params_changed, bool stop_req);
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/**
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* dpu_core_perf_crtc_release_bw - release bandwidth of the given crtc
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* @crtc: Pointer to crtc
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*/
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void dpu_core_perf_crtc_release_bw(struct drm_crtc *crtc);
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/**
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* dpu_core_perf_destroy - destroy the given core performance context
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* @perf: Pointer to core performance context
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*/
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void dpu_core_perf_destroy(struct dpu_core_perf *perf);
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/**
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* dpu_core_perf_init - initialize the given core performance context
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* @perf: Pointer to core performance context
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* @dev: Pointer to drm device
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* @catalog: Pointer to catalog
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* @core_clk: pointer to core clock
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*/
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int dpu_core_perf_init(struct dpu_core_perf *perf,
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struct drm_device *dev,
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struct dpu_mdss_cfg *catalog,
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struct dss_clk *core_clk);
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struct dpu_kms;
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/**
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* dpu_core_perf_debugfs_init - initialize debugfs for core performance context
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* @dpu_kms: Pointer to the dpu_kms struct
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* @debugfs_parent: Pointer to parent debugfs
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*/
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int dpu_core_perf_debugfs_init(struct dpu_kms *dpu_kms, struct dentry *parent);
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#endif /* _DPU_CORE_PERF_H_ */
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