725 lines
21 KiB
C
725 lines
21 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DPU_HW_CATALOG_H
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#define _DPU_HW_CATALOG_H
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#include <linux/kernel.h>
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#include <linux/bug.h>
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#include <linux/bitmap.h>
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#include <linux/err.h>
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#include <drm/drmP.h>
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/**
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* Max hardware block count: For ex: max 12 SSPP pipes or
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* 5 ctl paths. In all cases, it can have max 12 hardware blocks
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* based on current design
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*/
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#define MAX_BLOCKS 12
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#define DPU_HW_VER(MAJOR, MINOR, STEP) (((MAJOR & 0xF) << 28) |\
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((MINOR & 0xFFF) << 16) |\
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(STEP & 0xFFFF))
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#define DPU_HW_MAJOR(rev) ((rev) >> 28)
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#define DPU_HW_MINOR(rev) (((rev) >> 16) & 0xFFF)
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#define DPU_HW_STEP(rev) ((rev) & 0xFFFF)
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#define DPU_HW_MAJOR_MINOR(rev) ((rev) >> 16)
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#define IS_DPU_MAJOR_MINOR_SAME(rev1, rev2) \
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(DPU_HW_MAJOR_MINOR((rev1)) == DPU_HW_MAJOR_MINOR((rev2)))
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#define DPU_HW_VER_170 DPU_HW_VER(1, 7, 0) /* 8996 v1.0 */
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#define DPU_HW_VER_171 DPU_HW_VER(1, 7, 1) /* 8996 v2.0 */
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#define DPU_HW_VER_172 DPU_HW_VER(1, 7, 2) /* 8996 v3.0 */
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#define DPU_HW_VER_300 DPU_HW_VER(3, 0, 0) /* 8998 v1.0 */
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#define DPU_HW_VER_301 DPU_HW_VER(3, 0, 1) /* 8998 v1.1 */
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#define DPU_HW_VER_400 DPU_HW_VER(4, 0, 0) /* sdm845 v1.0 */
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#define DPU_HW_VER_401 DPU_HW_VER(4, 0, 1) /* sdm845 v2.0 */
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#define DPU_HW_VER_410 DPU_HW_VER(4, 1, 0) /* sdm670 v1.0 */
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#define DPU_HW_VER_500 DPU_HW_VER(5, 0, 0) /* sdm855 v1.0 */
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#define IS_MSM8996_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_170)
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#define IS_MSM8998_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_300)
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#define IS_SDM845_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_400)
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#define IS_SDM670_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_410)
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#define IS_SDM855_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_500)
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#define DPU_HW_BLK_NAME_LEN 16
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#define MAX_IMG_WIDTH 0x3fff
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#define MAX_IMG_HEIGHT 0x3fff
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#define CRTC_DUAL_MIXERS 2
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#define MAX_XIN_COUNT 16
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/**
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* Supported UBWC feature versions
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*/
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enum {
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DPU_HW_UBWC_VER_10 = 0x100,
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DPU_HW_UBWC_VER_20 = 0x200,
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DPU_HW_UBWC_VER_30 = 0x300,
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};
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#define IS_UBWC_20_SUPPORTED(rev) ((rev) >= DPU_HW_UBWC_VER_20)
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/**
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* MDP TOP BLOCK features
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* @DPU_MDP_PANIC_PER_PIPE Panic configuration needs to be be done per pipe
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* @DPU_MDP_10BIT_SUPPORT, Chipset supports 10 bit pixel formats
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* @DPU_MDP_BWC, MDSS HW supports Bandwidth compression.
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* @DPU_MDP_UBWC_1_0, This chipsets supports Universal Bandwidth
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* compression initial revision
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* @DPU_MDP_UBWC_1_5, Universal Bandwidth compression version 1.5
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* @DPU_MDP_MAX Maximum value
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*/
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enum {
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DPU_MDP_PANIC_PER_PIPE = 0x1,
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DPU_MDP_10BIT_SUPPORT,
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DPU_MDP_BWC,
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DPU_MDP_UBWC_1_0,
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DPU_MDP_UBWC_1_5,
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DPU_MDP_MAX
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};
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/**
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* SSPP sub-blocks/features
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* @DPU_SSPP_SRC Src and fetch part of the pipes,
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* @DPU_SSPP_SCALER_QSEED2, QSEED2 algorithm support
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* @DPU_SSPP_SCALER_QSEED3, QSEED3 alogorithm support
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* @DPU_SSPP_SCALER_RGB, RGB Scaler, supported by RGB pipes
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* @DPU_SSPP_CSC, Support of Color space converion
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* @DPU_SSPP_CSC_10BIT, Support of 10-bit Color space conversion
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* @DPU_SSPP_CURSOR, SSPP can be used as a cursor layer
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* @DPU_SSPP_QOS, SSPP support QoS control, danger/safe/creq
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* @DPU_SSPP_QOS_8LVL, SSPP support 8-level QoS control
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* @DPU_SSPP_EXCL_RECT, SSPP supports exclusion rect
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* @DPU_SSPP_SMART_DMA_V1, SmartDMA 1.0 support
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* @DPU_SSPP_SMART_DMA_V2, SmartDMA 2.0 support
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* @DPU_SSPP_TS_PREFILL Supports prefill with traffic shaper
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* @DPU_SSPP_TS_PREFILL_REC1 Supports prefill with traffic shaper multirec
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* @DPU_SSPP_CDP Supports client driven prefetch
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* @DPU_SSPP_MAX maximum value
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*/
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enum {
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DPU_SSPP_SRC = 0x1,
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DPU_SSPP_SCALER_QSEED2,
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DPU_SSPP_SCALER_QSEED3,
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DPU_SSPP_SCALER_RGB,
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DPU_SSPP_CSC,
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DPU_SSPP_CSC_10BIT,
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DPU_SSPP_CURSOR,
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DPU_SSPP_QOS,
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DPU_SSPP_QOS_8LVL,
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DPU_SSPP_EXCL_RECT,
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DPU_SSPP_SMART_DMA_V1,
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DPU_SSPP_SMART_DMA_V2,
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DPU_SSPP_TS_PREFILL,
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DPU_SSPP_TS_PREFILL_REC1,
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DPU_SSPP_CDP,
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DPU_SSPP_MAX
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};
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/*
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* MIXER sub-blocks/features
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* @DPU_MIXER_LAYER Layer mixer layer blend configuration,
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* @DPU_MIXER_SOURCESPLIT Layer mixer supports source-split configuration
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* @DPU_MIXER_GC Gamma correction block
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* @DPU_DIM_LAYER Layer mixer supports dim layer
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* @DPU_MIXER_MAX maximum value
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*/
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enum {
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DPU_MIXER_LAYER = 0x1,
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DPU_MIXER_SOURCESPLIT,
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DPU_MIXER_GC,
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DPU_DIM_LAYER,
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DPU_MIXER_MAX
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};
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/**
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* PINGPONG sub-blocks
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* @DPU_PINGPONG_TE Tear check block
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* @DPU_PINGPONG_TE2 Additional tear check block for split pipes
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* @DPU_PINGPONG_SPLIT PP block supports split fifo
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* @DPU_PINGPONG_SLAVE PP block is a suitable slave for split fifo
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* @DPU_PINGPONG_DITHER, Dither blocks
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* @DPU_PINGPONG_MAX
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*/
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enum {
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DPU_PINGPONG_TE = 0x1,
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DPU_PINGPONG_TE2,
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DPU_PINGPONG_SPLIT,
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DPU_PINGPONG_SLAVE,
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DPU_PINGPONG_DITHER,
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DPU_PINGPONG_MAX
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};
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/**
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* CTL sub-blocks
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* @DPU_CTL_SPLIT_DISPLAY CTL supports video mode split display
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* @DPU_CTL_MAX
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*/
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enum {
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DPU_CTL_SPLIT_DISPLAY = 0x1,
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DPU_CTL_MAX
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};
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/**
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* VBIF sub-blocks and features
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* @DPU_VBIF_QOS_OTLIM VBIF supports OT Limit
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* @DPU_VBIF_QOS_REMAP VBIF supports QoS priority remap
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* @DPU_VBIF_MAX maximum value
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*/
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enum {
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DPU_VBIF_QOS_OTLIM = 0x1,
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DPU_VBIF_QOS_REMAP,
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DPU_VBIF_MAX
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};
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/**
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* MACRO DPU_HW_BLK_INFO - information of HW blocks inside DPU
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* @name: string name for debug purposes
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* @id: enum identifying this block
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* @base: register base offset to mdss
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* @len: length of hardware block
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* @features bit mask identifying sub-blocks/features
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*/
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#define DPU_HW_BLK_INFO \
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char name[DPU_HW_BLK_NAME_LEN]; \
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u32 id; \
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u32 base; \
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u32 len; \
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unsigned long features
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/**
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* MACRO DPU_HW_SUBBLK_INFO - information of HW sub-block inside DPU
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* @name: string name for debug purposes
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* @id: enum identifying this sub-block
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* @base: offset of this sub-block relative to the block
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* offset
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* @len register block length of this sub-block
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*/
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#define DPU_HW_SUBBLK_INFO \
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char name[DPU_HW_BLK_NAME_LEN]; \
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u32 id; \
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u32 base; \
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u32 len
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/**
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* struct dpu_src_blk: SSPP part of the source pipes
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* @info: HW register and features supported by this sub-blk
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*/
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struct dpu_src_blk {
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DPU_HW_SUBBLK_INFO;
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};
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/**
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* struct dpu_scaler_blk: Scaler information
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* @info: HW register and features supported by this sub-blk
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* @version: qseed block revision
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*/
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struct dpu_scaler_blk {
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DPU_HW_SUBBLK_INFO;
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u32 version;
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};
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struct dpu_csc_blk {
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DPU_HW_SUBBLK_INFO;
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};
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/**
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* struct dpu_pp_blk : Pixel processing sub-blk information
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* @info: HW register and features supported by this sub-blk
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* @version: HW Algorithm version
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*/
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struct dpu_pp_blk {
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DPU_HW_SUBBLK_INFO;
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u32 version;
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};
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/**
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* enum dpu_qos_lut_usage - define QoS LUT use cases
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*/
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enum dpu_qos_lut_usage {
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DPU_QOS_LUT_USAGE_LINEAR,
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DPU_QOS_LUT_USAGE_MACROTILE,
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DPU_QOS_LUT_USAGE_NRT,
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DPU_QOS_LUT_USAGE_MAX,
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};
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/**
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* struct dpu_qos_lut_entry - define QoS LUT table entry
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* @fl: fill level, or zero on last entry to indicate default lut
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* @lut: lut to use if equal to or less than fill level
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*/
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struct dpu_qos_lut_entry {
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u32 fl;
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u64 lut;
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};
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/**
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* struct dpu_qos_lut_tbl - define QoS LUT table
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* @nentry: number of entry in this table
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* @entries: Pointer to table entries
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*/
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struct dpu_qos_lut_tbl {
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u32 nentry;
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struct dpu_qos_lut_entry *entries;
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};
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/**
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* struct dpu_caps - define DPU capabilities
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* @max_mixer_width max layer mixer line width support.
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* @max_mixer_blendstages max layer mixer blend stages or
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* supported z order
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* @qseed_type qseed2 or qseed3 support.
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* @smart_dma_rev Supported version of SmartDMA feature.
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* @ubwc_version UBWC feature version (0x0 for not supported)
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* @has_src_split source split feature status
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* @has_dim_layer dim layer feature status
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* @has_idle_pc indicate if idle power collapse feature is supported
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*/
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struct dpu_caps {
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u32 max_mixer_width;
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u32 max_mixer_blendstages;
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u32 qseed_type;
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u32 smart_dma_rev;
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u32 ubwc_version;
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bool has_src_split;
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bool has_dim_layer;
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bool has_idle_pc;
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};
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/**
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* struct dpu_sspp_blks_common : SSPP sub-blocks common configuration
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* @maxwidth: max pixelwidth supported by this pipe
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* @pixel_ram_size: size of latency hiding and de-tiling buffer in bytes
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* @maxhdeciexp: max horizontal decimation supported by this pipe
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* (max is 2^value)
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* @maxvdeciexp: max vertical decimation supported by this pipe
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* (max is 2^value)
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*/
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struct dpu_sspp_blks_common {
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u32 maxlinewidth;
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u32 pixel_ram_size;
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u32 maxhdeciexp;
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u32 maxvdeciexp;
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};
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/**
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* struct dpu_sspp_sub_blks : SSPP sub-blocks
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* common: Pointer to common configurations shared by sub blocks
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* @creq_vblank: creq priority during vertical blanking
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* @danger_vblank: danger priority during vertical blanking
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* @maxdwnscale: max downscale ratio supported(without DECIMATION)
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* @maxupscale: maxupscale ratio supported
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* @smart_dma_priority: hw priority of rect1 of multirect pipe
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* @max_per_pipe_bw: maximum allowable bandwidth of this pipe in kBps
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* @src_blk:
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* @scaler_blk:
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* @csc_blk:
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* @hsic:
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* @memcolor:
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* @pcc_blk:
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* @igc_blk:
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* @format_list: Pointer to list of supported formats
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* @num_formats: Number of supported formats
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* @virt_format_list: Pointer to list of supported formats for virtual planes
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* @virt_num_formats: Number of supported formats for virtual planes
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*/
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struct dpu_sspp_sub_blks {
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const struct dpu_sspp_blks_common *common;
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u32 creq_vblank;
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u32 danger_vblank;
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u32 maxdwnscale;
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u32 maxupscale;
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u32 smart_dma_priority;
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u32 max_per_pipe_bw;
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struct dpu_src_blk src_blk;
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struct dpu_scaler_blk scaler_blk;
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struct dpu_pp_blk csc_blk;
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struct dpu_pp_blk hsic_blk;
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struct dpu_pp_blk memcolor_blk;
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struct dpu_pp_blk pcc_blk;
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struct dpu_pp_blk igc_blk;
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const u32 *format_list;
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u32 num_formats;
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const u32 *virt_format_list;
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u32 virt_num_formats;
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};
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/**
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* struct dpu_lm_sub_blks: information of mixer block
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* @maxwidth: Max pixel width supported by this mixer
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* @maxblendstages: Max number of blend-stages supported
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* @blendstage_base: Blend-stage register base offset
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* @gc: gamma correction block
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*/
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struct dpu_lm_sub_blks {
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u32 maxwidth;
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u32 maxblendstages;
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u32 blendstage_base[MAX_BLOCKS];
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struct dpu_pp_blk gc;
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};
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struct dpu_pingpong_sub_blks {
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struct dpu_pp_blk te;
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struct dpu_pp_blk te2;
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struct dpu_pp_blk dither;
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};
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/**
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* dpu_clk_ctrl_type - Defines top level clock control signals
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*/
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enum dpu_clk_ctrl_type {
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DPU_CLK_CTRL_NONE,
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DPU_CLK_CTRL_VIG0,
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DPU_CLK_CTRL_VIG1,
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DPU_CLK_CTRL_VIG2,
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DPU_CLK_CTRL_VIG3,
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DPU_CLK_CTRL_VIG4,
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DPU_CLK_CTRL_RGB0,
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DPU_CLK_CTRL_RGB1,
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DPU_CLK_CTRL_RGB2,
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DPU_CLK_CTRL_RGB3,
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DPU_CLK_CTRL_DMA0,
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DPU_CLK_CTRL_DMA1,
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DPU_CLK_CTRL_CURSOR0,
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DPU_CLK_CTRL_CURSOR1,
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DPU_CLK_CTRL_INLINE_ROT0_SSPP,
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DPU_CLK_CTRL_MAX,
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};
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/* struct dpu_clk_ctrl_reg : Clock control register
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* @reg_off: register offset
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* @bit_off: bit offset
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*/
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struct dpu_clk_ctrl_reg {
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u32 reg_off;
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u32 bit_off;
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};
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/* struct dpu_mdp_cfg : MDP TOP-BLK instance info
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* @id: index identifying this block
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* @base: register base offset to mdss
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* @features bit mask identifying sub-blocks/features
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* @highest_bank_bit: UBWC parameter
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* @ubwc_static: ubwc static configuration
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* @ubwc_swizzle: ubwc default swizzle setting
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* @clk_ctrls clock control register definition
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*/
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struct dpu_mdp_cfg {
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DPU_HW_BLK_INFO;
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u32 highest_bank_bit;
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u32 ubwc_static;
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u32 ubwc_swizzle;
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struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX];
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};
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/* struct dpu_mdp_cfg : MDP TOP-BLK instance info
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* @id: index identifying this block
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* @base: register base offset to mdss
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* @features bit mask identifying sub-blocks/features
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*/
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struct dpu_ctl_cfg {
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DPU_HW_BLK_INFO;
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};
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/**
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* struct dpu_sspp_cfg - information of source pipes
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* @id: index identifying this block
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* @base register offset of this block
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* @features bit mask identifying sub-blocks/features
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* @sblk: SSPP sub-blocks information
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* @xin_id: bus client identifier
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* @clk_ctrl clock control identifier
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* @type sspp type identifier
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*/
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struct dpu_sspp_cfg {
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DPU_HW_BLK_INFO;
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const struct dpu_sspp_sub_blks *sblk;
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u32 xin_id;
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enum dpu_clk_ctrl_type clk_ctrl;
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u32 type;
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};
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/**
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* struct dpu_lm_cfg - information of layer mixer blocks
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* @id: index identifying this block
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* @base register offset of this block
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* @features bit mask identifying sub-blocks/features
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* @sblk: LM Sub-blocks information
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* @pingpong: ID of connected PingPong, PINGPONG_MAX if unsupported
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* @lm_pair_mask: Bitmask of LMs that can be controlled by same CTL
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*/
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struct dpu_lm_cfg {
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DPU_HW_BLK_INFO;
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const struct dpu_lm_sub_blks *sblk;
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u32 pingpong;
|
|
unsigned long lm_pair_mask;
|
|
};
|
|
|
|
/**
|
|
* struct dpu_pingpong_cfg - information of PING-PONG blocks
|
|
* @id enum identifying this block
|
|
* @base register offset of this block
|
|
* @features bit mask identifying sub-blocks/features
|
|
* @sblk sub-blocks information
|
|
*/
|
|
struct dpu_pingpong_cfg {
|
|
DPU_HW_BLK_INFO;
|
|
const struct dpu_pingpong_sub_blks *sblk;
|
|
};
|
|
|
|
/**
|
|
* struct dpu_intf_cfg - information of timing engine blocks
|
|
* @id enum identifying this block
|
|
* @base register offset of this block
|
|
* @features bit mask identifying sub-blocks/features
|
|
* @type: Interface type(DSI, DP, HDMI)
|
|
* @controller_id: Controller Instance ID in case of multiple of intf type
|
|
* @prog_fetch_lines_worst_case Worst case latency num lines needed to prefetch
|
|
*/
|
|
struct dpu_intf_cfg {
|
|
DPU_HW_BLK_INFO;
|
|
u32 type; /* interface type*/
|
|
u32 controller_id;
|
|
u32 prog_fetch_lines_worst_case;
|
|
};
|
|
|
|
/**
|
|
* struct dpu_vbif_dynamic_ot_cfg - dynamic OT setting
|
|
* @pps pixel per seconds
|
|
* @ot_limit OT limit to use up to specified pixel per second
|
|
*/
|
|
struct dpu_vbif_dynamic_ot_cfg {
|
|
u64 pps;
|
|
u32 ot_limit;
|
|
};
|
|
|
|
/**
|
|
* struct dpu_vbif_dynamic_ot_tbl - dynamic OT setting table
|
|
* @count length of cfg
|
|
* @cfg pointer to array of configuration settings with
|
|
* ascending requirements
|
|
*/
|
|
struct dpu_vbif_dynamic_ot_tbl {
|
|
u32 count;
|
|
struct dpu_vbif_dynamic_ot_cfg *cfg;
|
|
};
|
|
|
|
/**
|
|
* struct dpu_vbif_qos_tbl - QoS priority table
|
|
* @npriority_lvl num of priority level
|
|
* @priority_lvl pointer to array of priority level in ascending order
|
|
*/
|
|
struct dpu_vbif_qos_tbl {
|
|
u32 npriority_lvl;
|
|
u32 *priority_lvl;
|
|
};
|
|
|
|
/**
|
|
* struct dpu_vbif_cfg - information of VBIF blocks
|
|
* @id enum identifying this block
|
|
* @base register offset of this block
|
|
* @features bit mask identifying sub-blocks/features
|
|
* @ot_rd_limit default OT read limit
|
|
* @ot_wr_limit default OT write limit
|
|
* @xin_halt_timeout maximum time (in usec) for xin to halt
|
|
* @dynamic_ot_rd_tbl dynamic OT read configuration table
|
|
* @dynamic_ot_wr_tbl dynamic OT write configuration table
|
|
* @qos_rt_tbl real-time QoS priority table
|
|
* @qos_nrt_tbl non-real-time QoS priority table
|
|
* @memtype_count number of defined memtypes
|
|
* @memtype array of xin memtype definitions
|
|
*/
|
|
struct dpu_vbif_cfg {
|
|
DPU_HW_BLK_INFO;
|
|
u32 default_ot_rd_limit;
|
|
u32 default_ot_wr_limit;
|
|
u32 xin_halt_timeout;
|
|
struct dpu_vbif_dynamic_ot_tbl dynamic_ot_rd_tbl;
|
|
struct dpu_vbif_dynamic_ot_tbl dynamic_ot_wr_tbl;
|
|
struct dpu_vbif_qos_tbl qos_rt_tbl;
|
|
struct dpu_vbif_qos_tbl qos_nrt_tbl;
|
|
u32 memtype_count;
|
|
u32 memtype[MAX_XIN_COUNT];
|
|
};
|
|
/**
|
|
* struct dpu_reg_dma_cfg - information of lut dma blocks
|
|
* @id enum identifying this block
|
|
* @base register offset of this block
|
|
* @features bit mask identifying sub-blocks/features
|
|
* @version version of lutdma hw block
|
|
* @trigger_sel_off offset to trigger select registers of lutdma
|
|
*/
|
|
struct dpu_reg_dma_cfg {
|
|
DPU_HW_BLK_INFO;
|
|
u32 version;
|
|
u32 trigger_sel_off;
|
|
};
|
|
|
|
/**
|
|
* Define CDP use cases
|
|
* @DPU_PERF_CDP_UDAGE_RT: real-time use cases
|
|
* @DPU_PERF_CDP_USAGE_NRT: non real-time use cases such as WFD
|
|
*/
|
|
enum {
|
|
DPU_PERF_CDP_USAGE_RT,
|
|
DPU_PERF_CDP_USAGE_NRT,
|
|
DPU_PERF_CDP_USAGE_MAX
|
|
};
|
|
|
|
/**
|
|
* struct dpu_perf_cdp_cfg - define CDP use case configuration
|
|
* @rd_enable: true if read pipe CDP is enabled
|
|
* @wr_enable: true if write pipe CDP is enabled
|
|
*/
|
|
struct dpu_perf_cdp_cfg {
|
|
bool rd_enable;
|
|
bool wr_enable;
|
|
};
|
|
|
|
/**
|
|
* struct dpu_perf_cfg - performance control settings
|
|
* @max_bw_low low threshold of maximum bandwidth (kbps)
|
|
* @max_bw_high high threshold of maximum bandwidth (kbps)
|
|
* @min_core_ib minimum bandwidth for core (kbps)
|
|
* @min_core_ib minimum mnoc ib vote in kbps
|
|
* @min_llcc_ib minimum llcc ib vote in kbps
|
|
* @min_dram_ib minimum dram ib vote in kbps
|
|
* @core_ib_ff core instantaneous bandwidth fudge factor
|
|
* @core_clk_ff core clock fudge factor
|
|
* @comp_ratio_rt string of 0 or more of <fourcc>/<ven>/<mod>/<comp ratio>
|
|
* @comp_ratio_nrt string of 0 or more of <fourcc>/<ven>/<mod>/<comp ratio>
|
|
* @undersized_prefill_lines undersized prefill in lines
|
|
* @xtra_prefill_lines extra prefill latency in lines
|
|
* @dest_scale_prefill_lines destination scaler latency in lines
|
|
* @macrotile_perfill_lines macrotile latency in lines
|
|
* @yuv_nv12_prefill_lines yuv_nv12 latency in lines
|
|
* @linear_prefill_lines linear latency in lines
|
|
* @downscaling_prefill_lines downscaling latency in lines
|
|
* @amortizable_theshold minimum y position for traffic shaping prefill
|
|
* @min_prefill_lines minimum pipeline latency in lines
|
|
* @safe_lut_tbl: LUT tables for safe signals
|
|
* @danger_lut_tbl: LUT tables for danger signals
|
|
* @qos_lut_tbl: LUT tables for QoS signals
|
|
* @cdp_cfg cdp use case configurations
|
|
*/
|
|
struct dpu_perf_cfg {
|
|
u32 max_bw_low;
|
|
u32 max_bw_high;
|
|
u32 min_core_ib;
|
|
u32 min_llcc_ib;
|
|
u32 min_dram_ib;
|
|
const char *core_ib_ff;
|
|
const char *core_clk_ff;
|
|
const char *comp_ratio_rt;
|
|
const char *comp_ratio_nrt;
|
|
u32 undersized_prefill_lines;
|
|
u32 xtra_prefill_lines;
|
|
u32 dest_scale_prefill_lines;
|
|
u32 macrotile_prefill_lines;
|
|
u32 yuv_nv12_prefill_lines;
|
|
u32 linear_prefill_lines;
|
|
u32 downscaling_prefill_lines;
|
|
u32 amortizable_threshold;
|
|
u32 min_prefill_lines;
|
|
u32 safe_lut_tbl[DPU_QOS_LUT_USAGE_MAX];
|
|
u32 danger_lut_tbl[DPU_QOS_LUT_USAGE_MAX];
|
|
struct dpu_qos_lut_tbl qos_lut_tbl[DPU_QOS_LUT_USAGE_MAX];
|
|
struct dpu_perf_cdp_cfg cdp_cfg[DPU_PERF_CDP_USAGE_MAX];
|
|
};
|
|
|
|
/**
|
|
* struct dpu_mdss_cfg - information of MDSS HW
|
|
* This is the main catalog data structure representing
|
|
* this HW version. Contains number of instances,
|
|
* register offsets, capabilities of the all MDSS HW sub-blocks.
|
|
*
|
|
* @dma_formats Supported formats for dma pipe
|
|
* @cursor_formats Supported formats for cursor pipe
|
|
* @vig_formats Supported formats for vig pipe
|
|
*/
|
|
struct dpu_mdss_cfg {
|
|
u32 hwversion;
|
|
|
|
const struct dpu_caps *caps;
|
|
|
|
u32 mdp_count;
|
|
struct dpu_mdp_cfg *mdp;
|
|
|
|
u32 ctl_count;
|
|
struct dpu_ctl_cfg *ctl;
|
|
|
|
u32 sspp_count;
|
|
struct dpu_sspp_cfg *sspp;
|
|
|
|
u32 mixer_count;
|
|
struct dpu_lm_cfg *mixer;
|
|
|
|
u32 pingpong_count;
|
|
struct dpu_pingpong_cfg *pingpong;
|
|
|
|
u32 intf_count;
|
|
struct dpu_intf_cfg *intf;
|
|
|
|
u32 vbif_count;
|
|
struct dpu_vbif_cfg *vbif;
|
|
|
|
u32 reg_dma_count;
|
|
struct dpu_reg_dma_cfg dma_cfg;
|
|
|
|
u32 ad_count;
|
|
|
|
/* Add additional block data structures here */
|
|
|
|
struct dpu_perf_cfg perf;
|
|
struct dpu_format_extended *dma_formats;
|
|
struct dpu_format_extended *cursor_formats;
|
|
struct dpu_format_extended *vig_formats;
|
|
};
|
|
|
|
struct dpu_mdss_hw_cfg_handler {
|
|
u32 hw_rev;
|
|
void (*cfg_init)(struct dpu_mdss_cfg *dpu_cfg);
|
|
};
|
|
|
|
/*
|
|
* Access Macros
|
|
*/
|
|
#define BLK_MDP(s) ((s)->mdp)
|
|
#define BLK_CTL(s) ((s)->ctl)
|
|
#define BLK_VIG(s) ((s)->vig)
|
|
#define BLK_RGB(s) ((s)->rgb)
|
|
#define BLK_DMA(s) ((s)->dma)
|
|
#define BLK_CURSOR(s) ((s)->cursor)
|
|
#define BLK_MIXER(s) ((s)->mixer)
|
|
#define BLK_PINGPONG(s) ((s)->pingpong)
|
|
#define BLK_INTF(s) ((s)->intf)
|
|
#define BLK_AD(s) ((s)->ad)
|
|
|
|
/**
|
|
* dpu_hw_catalog_init - dpu hardware catalog init API retrieves
|
|
* hardcoded target specific catalog information in config structure
|
|
* @hw_rev: caller needs provide the hardware revision.
|
|
*
|
|
* Return: dpu config structure
|
|
*/
|
|
struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev);
|
|
|
|
/**
|
|
* dpu_hw_catalog_deinit - dpu hardware catalog cleanup
|
|
* @dpu_cfg: pointer returned from init function
|
|
*/
|
|
void dpu_hw_catalog_deinit(struct dpu_mdss_cfg *dpu_cfg);
|
|
|
|
#endif /* _DPU_HW_CATALOG_H */
|