fb2af0020a
Pull ARM updates from Russell King:
"This contains the usual updates from other people (listed below) and
the usual random muddle of miscellaneous ARM updates which cover some
low priority bug fixes and performance improvements.
I've started to put the pull request wording into the merge commits,
which are:
- NoMMU stuff:
This includes the following series sent earlier to the list:
- nommu-fixes
- R7 Support
- MPU support
I've left out the ARCH_MULTIPLATFORM/!MMU stuff that Arnd and I
were discussing today until we've reached a conclusion/that's had
some more review.
This is rebased (and re-tested) on your devel-stable branch because
otherwise there were going to be conflicts with Uwe's V7M work now
that you've merged that. I've included the fix for limiting MPU to
CPU_V7.
- Huge page support
These changes bring both HugeTLB support and Transparent HugePage
(THP) support to ARM. Only long descriptors (LPAE) are supported
in this series.
The code has been tested on an Arndale board (Exynos 5250).
- LPAE updates
Please pull these miscellaneous LPAE fixes I've been collecting for
a while now for 3.11. They've been tested and reviewed by quite a
few people, and most of the patches are pretty trivial. -- Will Deacon.
- arch_timer cleanups
Please pull these arch_timer cleanups I've been holding onto for a
while. They're the same as my last posting, but have been rebased
to v3.10-rc3.
- mpidr linearisation (multiprocessor id register - identifies which
CPU number we are in the system)
This patch series that implements MPIDR linearization through a
simple hashing algorithm and updates current cpu_{suspend}/{resume}
code to use the newly created hash structures to retrieve context
pointers. It represents a stepping stone for the implementation of
power management code on forthcoming multi-cluster ARM systems.
It has been tested on TC2 (dual cluster A15xA7 system), iMX6q,
OMAP4 and Tegra, with processors hitting low-power states requiring
warm-boot resume through the cpu_resume code path"
* 'for-linus' of git://git.linaro.org/people/rmk/linux-arm: (77 commits)
ARM: 7775/1: mm: Remove do_sect_fault from LPAE code
ARM: 7777/1: Avoid extra calls to the C compiler
ARM: 7774/1: Fix dtb dependency to use order-only prerequisites
ARM: 7770/1: remove residual ARMv2 support from decompressor
ARM: 7769/1: Cortex-A15: fix erratum 798181 implementation
ARM: 7768/1: prevent risks of out-of-bound access in ASID allocator
ARM: 7767/1: let the ASID allocator handle suspended animation
ARM: 7766/1: versatile: don't mark pen as __INIT
ARM: 7765/1: perf: Record the user-mode PC in the call chain.
ARM: 7735/2: Preserve the user r/w register TPIDRURW on context switch and fork
ARM: kernel: implement stack pointer save array through MPIDR hashing
ARM: kernel: build MPIDR hash function data structure
ARM: mpu: Ensure that MPU depends on CPU_V7
ARM: mpu: protect the vectors page with an MPU region
ARM: mpu: Allow enabling of the MPU via kconfig
ARM: 7758/1: introduce config HAS_BANDGAP
ARM: 7757/1: mm: don't flush icache in switch_mm with hardware broadcasting
ARM: 7751/1: zImage: don't overwrite ourself with a page table
ARM: 7749/1: spinlock: retry trylock operation if strex fails on free lock
ARM: 7748/1: oabi: handle faults when loading swi instruction from userspace
...
95 lines
2.2 KiB
Plaintext
95 lines
2.2 KiB
Plaintext
/*
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* Copyright (C) 2012 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include "skeleton.dtsi"
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/ {
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model = "BCM11351 SoC";
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compatible = "bcm,bcm11351";
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interrupt-parent = <&gic>;
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chosen {
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bootargs = "console=ttyS0,115200n8";
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};
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gic: interrupt-controller@3ff00100 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x3ff01000 0x1000>,
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<0x3ff00100 0x100>;
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};
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smc@0x3404c000 {
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compatible = "bcm,bcm11351-smc", "bcm,kona-smc";
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reg = <0x3404c000 0x400>; /* 1 KiB in SRAM */
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};
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uart@3e000000 {
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compatible = "bcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
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status = "disabled";
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reg = <0x3e000000 0x1000>;
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clock-frequency = <13000000>;
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interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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L2: l2-cache {
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compatible = "bcm,bcm11351-a2-pl310-cache";
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reg = <0x3ff20000 0x1000>;
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cache-unified;
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cache-level = <2>;
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};
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timer@35006000 {
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compatible = "bcm,kona-timer";
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reg = <0x35006000 0x1000>;
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interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <32768>;
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};
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sdio0: sdio@0x3f180000 {
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compatible = "bcm,kona-sdhci";
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reg = <0x3f180000 0x10000>;
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interrupts = <0x0 77 0x4>;
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status = "disabled";
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};
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sdio1: sdio@0x3f190000 {
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compatible = "bcm,kona-sdhci";
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reg = <0x3f190000 0x10000>;
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interrupts = <0x0 76 0x4>;
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status = "disabled";
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};
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sdio2: sdio@0x3f1a0000 {
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compatible = "bcm,kona-sdhci";
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reg = <0x3f1a0000 0x10000>;
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interrupts = <0x0 74 0x4>;
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status = "disabled";
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};
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sdio3: sdio@0x3f1b0000 {
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compatible = "bcm,kona-sdhci";
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reg = <0x3f1b0000 0x10000>;
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interrupts = <0x0 73 0x4>;
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status = "disabled";
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};
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};
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