29c7f3e68e
The DREQE bit of the DnFIFOSEL should be set to 1 after the DE bit of
USB-DMAC on R-Car SoCs is set to 1 after the USB-DMAC received a
zero-length packet. Otherwise, a transfer completion interruption
of USB-DMAC doesn't happen. Even if the driver changes the sequence,
normal operations (transmit/receive without zero-length packet) will
not cause any side-effects. So, this patch fixes the sequence anyway.
Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
[shimoda: revise the commit log]
Fixes:
|
||
|---|---|---|
| .. | ||
| common.c | ||
| common.h | ||
| fifo.c | ||
| fifo.h | ||
| Kconfig | ||
| Makefile | ||
| mod.c | ||
| mod.h | ||
| mod_gadget.c | ||
| mod_host.c | ||
| pipe.c | ||
| pipe.h | ||
| rcar2.c | ||
| rcar2.h | ||
| rcar3.c | ||
| rcar3.h | ||