ff6fd1478c
Enable ECC for Arria10 L2 cache on machine startup. The ECC has to be enabled before data is stored in memory otherwise the ECC will fail on reads. Use DT_MACHINE to select Arria10 L2 cache function. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: devicetree@vger.kernel.org Cc: dinguyen@opensource.altera.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux@arm.linux.org.uk Cc: linux-edac <linux-edac@vger.kernel.org> Link: http://lkml.kernel.org/r/1458576106-24505-9-git-send-email-tthayer@opensource.altera.com Signed-off-by: Borislav Petkov <bp@suse.de>
91 lines
2.6 KiB
C
91 lines
2.6 KiB
C
/*
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* Copyright Altera Corporation (C) 2016. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/io.h>
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#include <linux/of_platform.h>
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#include <linux/of_address.h>
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#include "core.h"
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/* A10 System Manager L2 ECC Control register */
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#define A10_MPU_CTRL_L2_ECC_OFST 0x0
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#define A10_MPU_CTRL_L2_ECC_EN BIT(0)
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/* A10 System Manager Global IRQ Mask register */
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#define A10_SYSMGR_ECC_INTMASK_CLR_OFST 0x98
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#define A10_SYSMGR_ECC_INTMASK_CLR_L2 BIT(0)
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/* A10 System Manager L2 ECC IRQ Clear register */
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#define A10_SYSMGR_MPU_CLEAR_L2_ECC_OFST 0xA8
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#define A10_SYSMGR_MPU_CLEAR_L2_ECC (BIT(31) | BIT(15))
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void socfpga_init_l2_ecc(void)
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{
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struct device_node *np;
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void __iomem *mapped_l2_edac_addr;
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np = of_find_compatible_node(NULL, NULL, "altr,socfpga-l2-ecc");
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if (!np) {
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pr_err("Unable to find socfpga-l2-ecc in dtb\n");
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return;
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}
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mapped_l2_edac_addr = of_iomap(np, 0);
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of_node_put(np);
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if (!mapped_l2_edac_addr) {
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pr_err("Unable to find L2 ECC mapping in dtb\n");
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return;
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}
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/* Enable ECC */
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writel(0x01, mapped_l2_edac_addr);
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iounmap(mapped_l2_edac_addr);
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}
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void socfpga_init_arria10_l2_ecc(void)
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{
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struct device_node *np;
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void __iomem *mapped_l2_edac_addr;
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/* Find the L2 EDAC device tree node */
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np = of_find_compatible_node(NULL, NULL, "altr,socfpga-a10-l2-ecc");
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if (!np) {
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pr_err("Unable to find socfpga-a10-l2-ecc in dtb\n");
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return;
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}
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mapped_l2_edac_addr = of_iomap(np, 0);
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of_node_put(np);
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if (!mapped_l2_edac_addr) {
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pr_err("Unable to find L2 ECC mapping in dtb\n");
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return;
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}
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if (!sys_manager_base_addr) {
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pr_err("System Mananger not mapped for L2 ECC\n");
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goto exit;
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}
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/* Clear any pending IRQs */
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writel(A10_SYSMGR_MPU_CLEAR_L2_ECC, (sys_manager_base_addr +
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A10_SYSMGR_MPU_CLEAR_L2_ECC_OFST));
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/* Enable ECC */
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writel(A10_SYSMGR_ECC_INTMASK_CLR_L2, sys_manager_base_addr +
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A10_SYSMGR_ECC_INTMASK_CLR_OFST);
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writel(A10_MPU_CTRL_L2_ECC_EN, mapped_l2_edac_addr +
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A10_MPU_CTRL_L2_ECC_OFST);
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exit:
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iounmap(mapped_l2_edac_addr);
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}
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