ee1a8d402e
These changes from 30 individual branches for the most part update device tree files, but there are also a few source code changes that have crept in this time, usually in order to atomically move over a driver from using hardcoded data to DT probing. A number of platforms change their DT files to use the C preprocessor, which is causing a bit of churn, but that is hopefully only this once. There are a few conflicts with the other branches unfortunately: * in exynos5440.dtsi and kirkwood-6281.dtsi, device nodes are added from multiple branches. Need to be careful to have the right set of closing braces as git gets this one wrong. * In kirkwood.dtsi, one 'ranges' line got split into two lines, while another line got added. Order of the lines does not matter. * in sama5d3.dtsi, some cleanup was merged the wrong way, causing a bogus conflict. We want the 'dmas' and 'dma-names' properties to get added here. * Two lines got removed independently in arch/arm/mach-mxs/mach-mxs.c * Contents get added independently in arch/arm/mach-omap2/cclock33xx_data.c -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIVAwUAUdLnpGCrR//JCVInAQI50RAAsXbH1SGvjKJemXhRkFloPDYpCbgdDUFr ChUbjNV1xsY/jaNCfMa5/Qo7lgz/Ot7BpJef9fZn7ret+dc7nchqe/4iIkAokAUh E4ao9D1dP5aAA0ihdbSQHCZtR/0SUR81h6BoOVuo/1mvEiBaFbWAeYe8/6LJd9II OU1w9bDmjfZWYFUXs+j2VF76ueZQ+kz69XDKZUGtkqN76m1AL8lGDurj5jxvyllF VJns8d9q2nr2q9PferfajK6rkOIPaTpwKblxZHUgobCyOitZaiZM0NgF733TsNM6 HXmhDhkcn7T81+SiHVfigJ/nxo9UgU4zNJCODF3WZIwGIj3FbxvCOpdCYi2NhCO8 oLcgDk57tpoKpB3gvAmYVQHP9FIepFa/WAWyPIADA7PkpYrwgc4v+cLEHXpd8SRv viLLIa5QuNdMeaK+Md9OKmKZFd7uFD9jiMtmdm6IpEVDDjMgoteb2XSoEtNebmtY MfbW4okn118a2dFKKaPTKcXVW/a5FRp2JGfB0A58RQHaJWj3JsY1bFn/xWPEpTOA IWB/HHMln0LYTL2AXN9HcaL1jnGI1Wq5eWBurX+cXQ/ij1A6jfoRKYglx7AQqOHj iWcGYtKLLJCgiWFnLSwcljZhfoYr0/z7rhns6yo7/vhN0riy+M84OgN4HbAmUzc1 Bgy9PnJTNo8= =8PtJ -----END PGP SIGNATURE----- Merge tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC device tree changes from Arnd Bergmann: "These changes from 30 individual branches for the most part update device tree files, but there are also a few source code changes that have crept in this time, usually in order to atomically move over a driver from using hardcoded data to DT probing. A number of platforms change their DT files to use the C preprocessor, which is causing a bit of churn, but that is hopefully only this once" * tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (372 commits) ARM: at91: dt: rm9200ek: add spi support ARM: at91: dt: rm9200: add spi support ARM: at91/DT: at91sam9n12: add SPI DMA client infos ARM: at91/DT: sama5d3: add SPI DMA client infos ARM: at91/DT: fix SPI compatibility string ARM: Kirkwood: Fix the internal register ranges translation ARM: dts: bcm281xx: change comment to C89 style ARM: mmc: bcm281xx SDHCI driver (dt mods) ARM: nomadik: add the new clocks to the device tree clk: nomadik: implement the Nomadik clocks properly ARM: dts: omap5-uevm: Provide USB Host PHY clock frequency ARM: dts: omap4-panda: Fix DVI EDID reads ARM: dts: omap4-panda: Add USB Host support arm: mvebu: enable mini-PCIe connectors on Armada 370 RD ARM: shmobile: irqpin: add a DT property to enable masking on parent ARM: dts: AM43x EPOS EVM support ARM: dts: OMAP5: Add bandgap DT entry ARM: dts: AM33XX: Add pinmux configuration for CPSW to am335x EVM ARM: dts: AM33XX: Add pinmux configuration for CPSW to EVMsk ARM: dts: AM33XX: Add pinmux configuration for CPSW to beaglebone ...
307 lines
7.7 KiB
Plaintext
307 lines
7.7 KiB
Plaintext
/*
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* Device Tree Include file for Marvell Armada XP family SoC
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*
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* Copyright (C) 2012 Marvell
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*
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* Contains definitions specific to the Armada XP MV78460 SoC that are not
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* common to all Armada XP SoCs.
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*/
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/include/ "armada-xp.dtsi"
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/ {
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model = "Marvell Armada XP MV78460 SoC";
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compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
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aliases {
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gpio0 = &gpio0;
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gpio1 = &gpio1;
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gpio2 = &gpio2;
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eth3 = ð3;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "marvell,sheeva-v7";
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reg = <0>;
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clocks = <&cpuclk 0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "marvell,sheeva-v7";
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reg = <1>;
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clocks = <&cpuclk 1>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "marvell,sheeva-v7";
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reg = <2>;
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clocks = <&cpuclk 2>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "marvell,sheeva-v7";
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reg = <3>;
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clocks = <&cpuclk 3>;
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};
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};
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soc {
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internal-regs {
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pinctrl {
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compatible = "marvell,mv78460-pinctrl";
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reg = <0x18000 0x38>;
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sdio_pins: sdio-pins {
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marvell,pins = "mpp30", "mpp31", "mpp32",
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"mpp33", "mpp34", "mpp35";
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marvell,function = "sd0";
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};
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};
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gpio0: gpio@18100 {
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compatible = "marvell,orion-gpio";
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reg = <0x18100 0x40>;
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ngpios = <32>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupts-cells = <2>;
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interrupts = <82>, <83>, <84>, <85>;
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};
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gpio1: gpio@18140 {
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compatible = "marvell,orion-gpio";
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reg = <0x18140 0x40>;
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ngpios = <32>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupts-cells = <2>;
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interrupts = <87>, <88>, <89>, <90>;
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};
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gpio2: gpio@18180 {
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compatible = "marvell,orion-gpio";
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reg = <0x18180 0x40>;
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ngpios = <3>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupts-cells = <2>;
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interrupts = <91>;
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};
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eth3: ethernet@34000 {
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compatible = "marvell,armada-370-neta";
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reg = <0x34000 0x4000>;
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interrupts = <14>;
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clocks = <&gateclk 1>;
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status = "disabled";
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};
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/*
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* MV78460 has 4 PCIe units Gen2.0: Two units can be
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* configured as x4 or quad x1 lanes. Two units are
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* x4/x1.
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*/
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pcie-controller {
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compatible = "marvell,armada-xp-pcie";
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status = "disabled";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x00 0xff>;
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ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
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0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
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0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
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0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
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0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
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0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
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0x82000000 0 0x82000 0x82000 0 0x00002000 /* Port 3.0 registers */
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0x82000000 0 0x84000 0x84000 0 0x00002000 /* Port 1.1 registers */
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0x82000000 0 0x88000 0x88000 0 0x00002000 /* Port 1.2 registers */
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0x82000000 0 0x8c000 0x8c000 0 0x00002000 /* Port 1.3 registers */
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0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
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0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
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pcie@1,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
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reg = <0x0800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 58>;
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marvell,pcie-port = <0>;
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marvell,pcie-lane = <0>;
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clocks = <&gateclk 5>;
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status = "disabled";
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};
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pcie@2,0 {
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device_type = "pci";
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assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
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reg = <0x1000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 59>;
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marvell,pcie-port = <0>;
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marvell,pcie-lane = <1>;
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clocks = <&gateclk 6>;
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status = "disabled";
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};
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pcie@3,0 {
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device_type = "pci";
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assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
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reg = <0x1800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 60>;
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marvell,pcie-port = <0>;
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marvell,pcie-lane = <2>;
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clocks = <&gateclk 7>;
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status = "disabled";
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};
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pcie@4,0 {
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device_type = "pci";
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assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
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reg = <0x2000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 61>;
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marvell,pcie-port = <0>;
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marvell,pcie-lane = <3>;
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clocks = <&gateclk 8>;
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status = "disabled";
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};
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pcie@5,0 {
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device_type = "pci";
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assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
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reg = <0x2800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 62>;
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marvell,pcie-port = <1>;
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marvell,pcie-lane = <0>;
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clocks = <&gateclk 9>;
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status = "disabled";
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};
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pcie@6,0 {
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device_type = "pci";
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assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
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reg = <0x3000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 63>;
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marvell,pcie-port = <1>;
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marvell,pcie-lane = <1>;
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clocks = <&gateclk 10>;
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status = "disabled";
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};
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pcie@7,0 {
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device_type = "pci";
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assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
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reg = <0x3800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 64>;
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marvell,pcie-port = <1>;
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marvell,pcie-lane = <2>;
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clocks = <&gateclk 11>;
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status = "disabled";
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};
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pcie@8,0 {
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device_type = "pci";
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assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
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reg = <0x4000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 65>;
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marvell,pcie-port = <1>;
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marvell,pcie-lane = <3>;
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clocks = <&gateclk 12>;
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status = "disabled";
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};
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pcie@9,0 {
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device_type = "pci";
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assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
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reg = <0x4800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 99>;
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marvell,pcie-port = <2>;
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marvell,pcie-lane = <0>;
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clocks = <&gateclk 26>;
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status = "disabled";
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};
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pcie@10,0 {
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device_type = "pci";
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assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
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reg = <0x5000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 103>;
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marvell,pcie-port = <3>;
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marvell,pcie-lane = <0>;
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clocks = <&gateclk 27>;
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status = "disabled";
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};
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};
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};
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};
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};
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