![Linus Torvalds](/assets/img/avatar_default.png)
Pull slave-dmaengine updates from Vinod Koul: "This time we have Andy updates on dw_dmac which is attempting to make this IP block available as PCI and platform device though not fully complete this time. We also have TI EDMA moving the dma driver to use dmaengine APIs, also have a new driver for mmp-tdma, along with bunch of small updates. Now for your excitement the merge is little unusual here, while merging the auto merge on linux-next picks wrong choice for pl330 (drivers/dma/pl330.c) and this causes build failure. The correct resolution is in linux-next. (DMA: PL330: Fix build error) I didn't back merge your tree this time as you are better than me so no point in doing that for me :)" Fixed the pl330 conflict as in linux-next, along with trivial header file conflicts due to changed includes. * 'next' of git://git.infradead.org/users/vkoul/slave-dma: (29 commits) dma: tegra: fix interrupt name issue with apb dma. dw_dmac: fix a regression in dwc_prep_dma_memcpy dw_dmac: introduce software emulation of LLP transfers dw_dmac: autoconfigure data_width or get it via platform data dw_dmac: autoconfigure block_size or use platform data dw_dmac: get number of channels from hardware if possible dw_dmac: fill optional encoded parameters in register structure dw_dmac: mark dwc_dump_chan_regs as inline DMA: PL330: return ENOMEM instead of 0 from pl330_alloc_chan_resources DMA: PL330: Remove redundant runtime_suspend/resume functions DMA: PL330: Remove controller clock enable/disable dmaengine: use kmem_cache_zalloc instead of kmem_cache_alloc/memset DMA: PL330: Set the capability of pdm0 and pdm1 as DMA_PRIVATE ARM: EXYNOS: Set the capability of pdm0 and pdm1 as DMA_PRIVATE dma: tegra: use list_move_tail instead of list_del/list_add_tail mxs/dma: Enlarge the CCW descriptor area to 4 pages dw_dmac: utilize slave_id to pass request line dmaengine: mmp_tdma: add dt support dmaengine: mmp-pdma support spi: davici - make davinci select edma ...
622 lines
15 KiB
C
622 lines
15 KiB
C
/*
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* Driver For Marvell Two-channel DMA Engine
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*
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* Copyright: Marvell International Ltd.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/dma-mapping.h>
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#include <linux/slab.h>
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#include <linux/dmaengine.h>
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#include <linux/platform_device.h>
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#include <linux/device.h>
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#include <mach/regs-icu.h>
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#include <linux/platform_data/dma-mmp_tdma.h>
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#include <linux/of_device.h>
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#include "dmaengine.h"
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/*
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* Two-Channel DMA registers
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*/
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#define TDBCR 0x00 /* Byte Count */
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#define TDSAR 0x10 /* Src Addr */
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#define TDDAR 0x20 /* Dst Addr */
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#define TDNDPR 0x30 /* Next Desc */
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#define TDCR 0x40 /* Control */
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#define TDCP 0x60 /* Priority*/
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#define TDCDPR 0x70 /* Current Desc */
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#define TDIMR 0x80 /* Int Mask */
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#define TDISR 0xa0 /* Int Status */
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/* Two-Channel DMA Control Register */
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#define TDCR_SSZ_8_BITS (0x0 << 22) /* Sample Size */
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#define TDCR_SSZ_12_BITS (0x1 << 22)
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#define TDCR_SSZ_16_BITS (0x2 << 22)
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#define TDCR_SSZ_20_BITS (0x3 << 22)
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#define TDCR_SSZ_24_BITS (0x4 << 22)
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#define TDCR_SSZ_32_BITS (0x5 << 22)
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#define TDCR_SSZ_SHIFT (0x1 << 22)
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#define TDCR_SSZ_MASK (0x7 << 22)
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#define TDCR_SSPMOD (0x1 << 21) /* SSP MOD */
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#define TDCR_ABR (0x1 << 20) /* Channel Abort */
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#define TDCR_CDE (0x1 << 17) /* Close Desc Enable */
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#define TDCR_PACKMOD (0x1 << 16) /* Pack Mode (ADMA Only) */
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#define TDCR_CHANACT (0x1 << 14) /* Channel Active */
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#define TDCR_FETCHND (0x1 << 13) /* Fetch Next Desc */
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#define TDCR_CHANEN (0x1 << 12) /* Channel Enable */
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#define TDCR_INTMODE (0x1 << 10) /* Interrupt Mode */
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#define TDCR_CHAINMOD (0x1 << 9) /* Chain Mode */
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#define TDCR_BURSTSZ_MSK (0x7 << 6) /* Burst Size */
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#define TDCR_BURSTSZ_4B (0x0 << 6)
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#define TDCR_BURSTSZ_8B (0x1 << 6)
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#define TDCR_BURSTSZ_16B (0x3 << 6)
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#define TDCR_BURSTSZ_32B (0x6 << 6)
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#define TDCR_BURSTSZ_64B (0x7 << 6)
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#define TDCR_BURSTSZ_SQU_32B (0x7 << 6)
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#define TDCR_BURSTSZ_128B (0x5 << 6)
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#define TDCR_DSTDIR_MSK (0x3 << 4) /* Dst Direction */
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#define TDCR_DSTDIR_ADDR_HOLD (0x2 << 4) /* Dst Addr Hold */
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#define TDCR_DSTDIR_ADDR_INC (0x0 << 4) /* Dst Addr Increment */
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#define TDCR_SRCDIR_MSK (0x3 << 2) /* Src Direction */
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#define TDCR_SRCDIR_ADDR_HOLD (0x2 << 2) /* Src Addr Hold */
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#define TDCR_SRCDIR_ADDR_INC (0x0 << 2) /* Src Addr Increment */
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#define TDCR_DSTDESCCONT (0x1 << 1)
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#define TDCR_SRCDESTCONT (0x1 << 0)
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/* Two-Channel DMA Int Mask Register */
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#define TDIMR_COMP (0x1 << 0)
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/* Two-Channel DMA Int Status Register */
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#define TDISR_COMP (0x1 << 0)
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/*
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* Two-Channel DMA Descriptor Struct
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* NOTE: desc's buf must be aligned to 16 bytes.
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*/
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struct mmp_tdma_desc {
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u32 byte_cnt;
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u32 src_addr;
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u32 dst_addr;
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u32 nxt_desc;
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};
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enum mmp_tdma_type {
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MMP_AUD_TDMA = 0,
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PXA910_SQU,
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};
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#define TDMA_ALIGNMENT 3
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#define TDMA_MAX_XFER_BYTES SZ_64K
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struct mmp_tdma_chan {
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struct device *dev;
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struct dma_chan chan;
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struct dma_async_tx_descriptor desc;
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struct tasklet_struct tasklet;
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struct mmp_tdma_desc *desc_arr;
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phys_addr_t desc_arr_phys;
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int desc_num;
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enum dma_transfer_direction dir;
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dma_addr_t dev_addr;
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u32 burst_sz;
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enum dma_slave_buswidth buswidth;
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enum dma_status status;
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int idx;
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enum mmp_tdma_type type;
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int irq;
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unsigned long reg_base;
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size_t buf_len;
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size_t period_len;
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size_t pos;
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};
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#define TDMA_CHANNEL_NUM 2
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struct mmp_tdma_device {
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struct device *dev;
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void __iomem *base;
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struct dma_device device;
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struct mmp_tdma_chan *tdmac[TDMA_CHANNEL_NUM];
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};
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#define to_mmp_tdma_chan(dchan) container_of(dchan, struct mmp_tdma_chan, chan)
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static void mmp_tdma_chan_set_desc(struct mmp_tdma_chan *tdmac, dma_addr_t phys)
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{
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writel(phys, tdmac->reg_base + TDNDPR);
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writel(readl(tdmac->reg_base + TDCR) | TDCR_FETCHND,
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tdmac->reg_base + TDCR);
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}
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static void mmp_tdma_enable_chan(struct mmp_tdma_chan *tdmac)
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{
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/* enable irq */
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writel(TDIMR_COMP, tdmac->reg_base + TDIMR);
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/* enable dma chan */
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writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN,
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tdmac->reg_base + TDCR);
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tdmac->status = DMA_IN_PROGRESS;
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}
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static void mmp_tdma_disable_chan(struct mmp_tdma_chan *tdmac)
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{
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writel(readl(tdmac->reg_base + TDCR) & ~TDCR_CHANEN,
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tdmac->reg_base + TDCR);
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tdmac->status = DMA_SUCCESS;
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}
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static void mmp_tdma_resume_chan(struct mmp_tdma_chan *tdmac)
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{
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writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN,
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tdmac->reg_base + TDCR);
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tdmac->status = DMA_IN_PROGRESS;
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}
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static void mmp_tdma_pause_chan(struct mmp_tdma_chan *tdmac)
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{
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writel(readl(tdmac->reg_base + TDCR) & ~TDCR_CHANEN,
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tdmac->reg_base + TDCR);
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tdmac->status = DMA_PAUSED;
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}
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static int mmp_tdma_config_chan(struct mmp_tdma_chan *tdmac)
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{
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unsigned int tdcr;
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mmp_tdma_disable_chan(tdmac);
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if (tdmac->dir == DMA_MEM_TO_DEV)
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tdcr = TDCR_DSTDIR_ADDR_HOLD | TDCR_SRCDIR_ADDR_INC;
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else if (tdmac->dir == DMA_DEV_TO_MEM)
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tdcr = TDCR_SRCDIR_ADDR_HOLD | TDCR_DSTDIR_ADDR_INC;
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if (tdmac->type == MMP_AUD_TDMA) {
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tdcr |= TDCR_PACKMOD;
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switch (tdmac->burst_sz) {
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case 4:
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tdcr |= TDCR_BURSTSZ_4B;
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break;
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case 8:
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tdcr |= TDCR_BURSTSZ_8B;
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break;
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case 16:
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tdcr |= TDCR_BURSTSZ_16B;
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break;
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case 32:
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tdcr |= TDCR_BURSTSZ_32B;
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break;
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case 64:
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tdcr |= TDCR_BURSTSZ_64B;
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break;
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case 128:
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tdcr |= TDCR_BURSTSZ_128B;
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break;
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default:
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dev_err(tdmac->dev, "mmp_tdma: unknown burst size.\n");
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return -EINVAL;
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}
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switch (tdmac->buswidth) {
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case DMA_SLAVE_BUSWIDTH_1_BYTE:
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tdcr |= TDCR_SSZ_8_BITS;
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break;
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case DMA_SLAVE_BUSWIDTH_2_BYTES:
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tdcr |= TDCR_SSZ_16_BITS;
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break;
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case DMA_SLAVE_BUSWIDTH_4_BYTES:
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tdcr |= TDCR_SSZ_32_BITS;
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break;
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default:
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dev_err(tdmac->dev, "mmp_tdma: unknown bus size.\n");
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return -EINVAL;
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}
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} else if (tdmac->type == PXA910_SQU) {
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tdcr |= TDCR_BURSTSZ_SQU_32B;
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tdcr |= TDCR_SSPMOD;
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}
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writel(tdcr, tdmac->reg_base + TDCR);
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return 0;
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}
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static int mmp_tdma_clear_chan_irq(struct mmp_tdma_chan *tdmac)
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{
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u32 reg = readl(tdmac->reg_base + TDISR);
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if (reg & TDISR_COMP) {
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/* clear irq */
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reg &= ~TDISR_COMP;
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writel(reg, tdmac->reg_base + TDISR);
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return 0;
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}
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return -EAGAIN;
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}
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static irqreturn_t mmp_tdma_chan_handler(int irq, void *dev_id)
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{
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struct mmp_tdma_chan *tdmac = dev_id;
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if (mmp_tdma_clear_chan_irq(tdmac) == 0) {
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tdmac->pos = (tdmac->pos + tdmac->period_len) % tdmac->buf_len;
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tasklet_schedule(&tdmac->tasklet);
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return IRQ_HANDLED;
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} else
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return IRQ_NONE;
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}
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static irqreturn_t mmp_tdma_int_handler(int irq, void *dev_id)
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{
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struct mmp_tdma_device *tdev = dev_id;
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int i, ret;
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int irq_num = 0;
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for (i = 0; i < TDMA_CHANNEL_NUM; i++) {
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struct mmp_tdma_chan *tdmac = tdev->tdmac[i];
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ret = mmp_tdma_chan_handler(irq, tdmac);
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if (ret == IRQ_HANDLED)
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irq_num++;
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}
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if (irq_num)
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return IRQ_HANDLED;
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else
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return IRQ_NONE;
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}
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static void dma_do_tasklet(unsigned long data)
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{
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struct mmp_tdma_chan *tdmac = (struct mmp_tdma_chan *)data;
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if (tdmac->desc.callback)
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tdmac->desc.callback(tdmac->desc.callback_param);
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}
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static void mmp_tdma_free_descriptor(struct mmp_tdma_chan *tdmac)
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{
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struct gen_pool *gpool;
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int size = tdmac->desc_num * sizeof(struct mmp_tdma_desc);
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gpool = sram_get_gpool("asram");
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if (tdmac->desc_arr)
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gen_pool_free(gpool, (unsigned long)tdmac->desc_arr,
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size);
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tdmac->desc_arr = NULL;
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return;
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}
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static dma_cookie_t mmp_tdma_tx_submit(struct dma_async_tx_descriptor *tx)
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{
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struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(tx->chan);
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mmp_tdma_chan_set_desc(tdmac, tdmac->desc_arr_phys);
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return 0;
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}
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static int mmp_tdma_alloc_chan_resources(struct dma_chan *chan)
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{
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struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
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int ret;
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dma_async_tx_descriptor_init(&tdmac->desc, chan);
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tdmac->desc.tx_submit = mmp_tdma_tx_submit;
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if (tdmac->irq) {
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ret = devm_request_irq(tdmac->dev, tdmac->irq,
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mmp_tdma_chan_handler, IRQF_DISABLED, "tdma", tdmac);
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if (ret)
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return ret;
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}
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return 1;
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}
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static void mmp_tdma_free_chan_resources(struct dma_chan *chan)
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{
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struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
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if (tdmac->irq)
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devm_free_irq(tdmac->dev, tdmac->irq, tdmac);
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mmp_tdma_free_descriptor(tdmac);
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return;
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}
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struct mmp_tdma_desc *mmp_tdma_alloc_descriptor(struct mmp_tdma_chan *tdmac)
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{
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struct gen_pool *gpool;
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int size = tdmac->desc_num * sizeof(struct mmp_tdma_desc);
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gpool = sram_get_gpool("asram");
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if (!gpool)
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return NULL;
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tdmac->desc_arr = (void *)gen_pool_alloc(gpool, size);
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if (!tdmac->desc_arr)
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return NULL;
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tdmac->desc_arr_phys = gen_pool_virt_to_phys(gpool,
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(unsigned long)tdmac->desc_arr);
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return tdmac->desc_arr;
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}
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static struct dma_async_tx_descriptor *mmp_tdma_prep_dma_cyclic(
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struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
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size_t period_len, enum dma_transfer_direction direction,
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unsigned long flags, void *context)
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{
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struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
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struct mmp_tdma_desc *desc;
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int num_periods = buf_len / period_len;
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int i = 0, buf = 0;
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if (tdmac->status != DMA_SUCCESS)
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return NULL;
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if (period_len > TDMA_MAX_XFER_BYTES) {
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dev_err(tdmac->dev,
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"maximum period size exceeded: %d > %d\n",
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period_len, TDMA_MAX_XFER_BYTES);
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goto err_out;
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}
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tdmac->status = DMA_IN_PROGRESS;
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tdmac->desc_num = num_periods;
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desc = mmp_tdma_alloc_descriptor(tdmac);
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if (!desc)
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goto err_out;
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while (buf < buf_len) {
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desc = &tdmac->desc_arr[i];
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if (i + 1 == num_periods)
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desc->nxt_desc = tdmac->desc_arr_phys;
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else
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desc->nxt_desc = tdmac->desc_arr_phys +
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sizeof(*desc) * (i + 1);
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if (direction == DMA_MEM_TO_DEV) {
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desc->src_addr = dma_addr;
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desc->dst_addr = tdmac->dev_addr;
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} else {
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desc->src_addr = tdmac->dev_addr;
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desc->dst_addr = dma_addr;
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}
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desc->byte_cnt = period_len;
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dma_addr += period_len;
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buf += period_len;
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i++;
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}
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tdmac->buf_len = buf_len;
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tdmac->period_len = period_len;
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tdmac->pos = 0;
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return &tdmac->desc;
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err_out:
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tdmac->status = DMA_ERROR;
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return NULL;
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}
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static int mmp_tdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
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unsigned long arg)
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{
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struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
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struct dma_slave_config *dmaengine_cfg = (void *)arg;
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int ret = 0;
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switch (cmd) {
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case DMA_TERMINATE_ALL:
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mmp_tdma_disable_chan(tdmac);
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break;
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case DMA_PAUSE:
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mmp_tdma_pause_chan(tdmac);
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break;
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case DMA_RESUME:
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mmp_tdma_resume_chan(tdmac);
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break;
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case DMA_SLAVE_CONFIG:
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if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
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tdmac->dev_addr = dmaengine_cfg->src_addr;
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tdmac->burst_sz = dmaengine_cfg->src_maxburst;
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tdmac->buswidth = dmaengine_cfg->src_addr_width;
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} else {
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tdmac->dev_addr = dmaengine_cfg->dst_addr;
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tdmac->burst_sz = dmaengine_cfg->dst_maxburst;
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tdmac->buswidth = dmaengine_cfg->dst_addr_width;
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}
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tdmac->dir = dmaengine_cfg->direction;
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return mmp_tdma_config_chan(tdmac);
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default:
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ret = -ENOSYS;
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}
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return ret;
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}
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static enum dma_status mmp_tdma_tx_status(struct dma_chan *chan,
|
|
dma_cookie_t cookie, struct dma_tx_state *txstate)
|
|
{
|
|
struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
|
|
|
|
dma_set_residue(txstate, tdmac->buf_len - tdmac->pos);
|
|
|
|
return tdmac->status;
|
|
}
|
|
|
|
static void mmp_tdma_issue_pending(struct dma_chan *chan)
|
|
{
|
|
struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
|
|
|
|
mmp_tdma_enable_chan(tdmac);
|
|
}
|
|
|
|
static int __devexit mmp_tdma_remove(struct platform_device *pdev)
|
|
{
|
|
struct mmp_tdma_device *tdev = platform_get_drvdata(pdev);
|
|
|
|
dma_async_device_unregister(&tdev->device);
|
|
return 0;
|
|
}
|
|
|
|
static int __devinit mmp_tdma_chan_init(struct mmp_tdma_device *tdev,
|
|
int idx, int irq, int type)
|
|
{
|
|
struct mmp_tdma_chan *tdmac;
|
|
|
|
if (idx >= TDMA_CHANNEL_NUM) {
|
|
dev_err(tdev->dev, "too many channels for device!\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* alloc channel */
|
|
tdmac = devm_kzalloc(tdev->dev, sizeof(*tdmac), GFP_KERNEL);
|
|
if (!tdmac) {
|
|
dev_err(tdev->dev, "no free memory for DMA channels!\n");
|
|
return -ENOMEM;
|
|
}
|
|
if (irq)
|
|
tdmac->irq = irq;
|
|
tdmac->dev = tdev->dev;
|
|
tdmac->chan.device = &tdev->device;
|
|
tdmac->idx = idx;
|
|
tdmac->type = type;
|
|
tdmac->reg_base = (unsigned long)tdev->base + idx * 4;
|
|
tdmac->status = DMA_SUCCESS;
|
|
tdev->tdmac[tdmac->idx] = tdmac;
|
|
tasklet_init(&tdmac->tasklet, dma_do_tasklet, (unsigned long)tdmac);
|
|
|
|
/* add the channel to tdma_chan list */
|
|
list_add_tail(&tdmac->chan.device_node,
|
|
&tdev->device.channels);
|
|
return 0;
|
|
}
|
|
|
|
static struct of_device_id mmp_tdma_dt_ids[] = {
|
|
{ .compatible = "marvell,adma-1.0", .data = (void *)MMP_AUD_TDMA},
|
|
{ .compatible = "marvell,pxa910-squ", .data = (void *)PXA910_SQU},
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, mmp_tdma_dt_ids);
|
|
|
|
static int __devinit mmp_tdma_probe(struct platform_device *pdev)
|
|
{
|
|
enum mmp_tdma_type type;
|
|
const struct of_device_id *of_id;
|
|
struct mmp_tdma_device *tdev;
|
|
struct resource *iores;
|
|
int i, ret;
|
|
int irq = 0, irq_num = 0;
|
|
int chan_num = TDMA_CHANNEL_NUM;
|
|
|
|
of_id = of_match_device(mmp_tdma_dt_ids, &pdev->dev);
|
|
if (of_id)
|
|
type = (enum mmp_tdma_type) of_id->data;
|
|
else
|
|
type = platform_get_device_id(pdev)->driver_data;
|
|
|
|
/* always have couple channels */
|
|
tdev = devm_kzalloc(&pdev->dev, sizeof(*tdev), GFP_KERNEL);
|
|
if (!tdev)
|
|
return -ENOMEM;
|
|
|
|
tdev->dev = &pdev->dev;
|
|
|
|
for (i = 0; i < chan_num; i++) {
|
|
if (platform_get_irq(pdev, i) > 0)
|
|
irq_num++;
|
|
}
|
|
|
|
iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!iores)
|
|
return -EINVAL;
|
|
|
|
tdev->base = devm_request_and_ioremap(&pdev->dev, iores);
|
|
if (!tdev->base)
|
|
return -EADDRNOTAVAIL;
|
|
|
|
INIT_LIST_HEAD(&tdev->device.channels);
|
|
|
|
if (irq_num != chan_num) {
|
|
irq = platform_get_irq(pdev, 0);
|
|
ret = devm_request_irq(&pdev->dev, irq,
|
|
mmp_tdma_int_handler, IRQF_DISABLED, "tdma", tdev);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
/* initialize channel parameters */
|
|
for (i = 0; i < chan_num; i++) {
|
|
irq = (irq_num != chan_num) ? 0 : platform_get_irq(pdev, i);
|
|
ret = mmp_tdma_chan_init(tdev, i, irq, type);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
dma_cap_set(DMA_SLAVE, tdev->device.cap_mask);
|
|
dma_cap_set(DMA_CYCLIC, tdev->device.cap_mask);
|
|
tdev->device.dev = &pdev->dev;
|
|
tdev->device.device_alloc_chan_resources =
|
|
mmp_tdma_alloc_chan_resources;
|
|
tdev->device.device_free_chan_resources =
|
|
mmp_tdma_free_chan_resources;
|
|
tdev->device.device_prep_dma_cyclic = mmp_tdma_prep_dma_cyclic;
|
|
tdev->device.device_tx_status = mmp_tdma_tx_status;
|
|
tdev->device.device_issue_pending = mmp_tdma_issue_pending;
|
|
tdev->device.device_control = mmp_tdma_control;
|
|
tdev->device.copy_align = TDMA_ALIGNMENT;
|
|
|
|
dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
|
|
platform_set_drvdata(pdev, tdev);
|
|
|
|
ret = dma_async_device_register(&tdev->device);
|
|
if (ret) {
|
|
dev_err(tdev->device.dev, "unable to register\n");
|
|
return ret;
|
|
}
|
|
|
|
dev_info(tdev->device.dev, "initialized\n");
|
|
return 0;
|
|
}
|
|
|
|
static const struct platform_device_id mmp_tdma_id_table[] = {
|
|
{ "mmp-adma", MMP_AUD_TDMA },
|
|
{ "pxa910-squ", PXA910_SQU },
|
|
{ },
|
|
};
|
|
|
|
static struct platform_driver mmp_tdma_driver = {
|
|
.driver = {
|
|
.name = "mmp-tdma",
|
|
.owner = THIS_MODULE,
|
|
.of_match_table = mmp_tdma_dt_ids,
|
|
},
|
|
.id_table = mmp_tdma_id_table,
|
|
.probe = mmp_tdma_probe,
|
|
.remove = __devexit_p(mmp_tdma_remove),
|
|
};
|
|
|
|
module_platform_driver(mmp_tdma_driver);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_DESCRIPTION("MMP Two-Channel DMA Driver");
|
|
MODULE_ALIAS("platform:mmp-tdma");
|
|
MODULE_AUTHOR("Leo Yan <leoy@marvell.com>");
|
|
MODULE_AUTHOR("Zhangfei Gao <zhangfei.gao@marvell.com>");
|