![Lorenzo Pieralisi](/assets/img/avatar_default.png)
This patch updates the topology initialization code to use the newly defined accessors to retrieve the MPIDR affinity levels. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Will Deacon <will.deacon@arm.com> Acked-by: Nicolas Pitre <nico@linaro.org>
314 lines
8.4 KiB
C
314 lines
8.4 KiB
C
/*
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* arch/arm/kernel/topology.c
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*
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* Copyright (C) 2011 Linaro Limited.
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* Written by: Vincent Guittot
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*
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* based on arch/sh/kernel/topology.c
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/cpu.h>
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#include <linux/cpumask.h>
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#include <linux/init.h>
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#include <linux/percpu.h>
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#include <linux/node.h>
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#include <linux/nodemask.h>
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#include <linux/of.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <asm/cputype.h>
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#include <asm/topology.h>
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/*
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* cpu power scale management
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*/
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/*
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* cpu power table
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* This per cpu data structure describes the relative capacity of each core.
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* On a heteregenous system, cores don't have the same computation capacity
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* and we reflect that difference in the cpu_power field so the scheduler can
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* take this difference into account during load balance. A per cpu structure
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* is preferred because each CPU updates its own cpu_power field during the
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* load balance except for idle cores. One idle core is selected to run the
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* rebalance_domains for all idle cores and the cpu_power can be updated
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* during this sequence.
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*/
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static DEFINE_PER_CPU(unsigned long, cpu_scale);
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unsigned long arch_scale_freq_power(struct sched_domain *sd, int cpu)
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{
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return per_cpu(cpu_scale, cpu);
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}
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static void set_power_scale(unsigned int cpu, unsigned long power)
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{
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per_cpu(cpu_scale, cpu) = power;
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}
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#ifdef CONFIG_OF
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struct cpu_efficiency {
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const char *compatible;
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unsigned long efficiency;
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};
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/*
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* Table of relative efficiency of each processors
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* The efficiency value must fit in 20bit and the final
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* cpu_scale value must be in the range
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* 0 < cpu_scale < 3*SCHED_POWER_SCALE/2
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* in order to return at most 1 when DIV_ROUND_CLOSEST
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* is used to compute the capacity of a CPU.
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* Processors that are not defined in the table,
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* use the default SCHED_POWER_SCALE value for cpu_scale.
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*/
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struct cpu_efficiency table_efficiency[] = {
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{"arm,cortex-a15", 3891},
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{"arm,cortex-a7", 2048},
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{NULL, },
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};
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struct cpu_capacity {
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unsigned long hwid;
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unsigned long capacity;
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};
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struct cpu_capacity *cpu_capacity;
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unsigned long middle_capacity = 1;
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/*
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* Iterate all CPUs' descriptor in DT and compute the efficiency
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* (as per table_efficiency). Also calculate a middle efficiency
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* as close as possible to (max{eff_i} - min{eff_i}) / 2
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* This is later used to scale the cpu_power field such that an
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* 'average' CPU is of middle power. Also see the comments near
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* table_efficiency[] and update_cpu_power().
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*/
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static void __init parse_dt_topology(void)
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{
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struct cpu_efficiency *cpu_eff;
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struct device_node *cn = NULL;
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unsigned long min_capacity = (unsigned long)(-1);
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unsigned long max_capacity = 0;
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unsigned long capacity = 0;
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int alloc_size, cpu = 0;
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alloc_size = nr_cpu_ids * sizeof(struct cpu_capacity);
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cpu_capacity = (struct cpu_capacity *)kzalloc(alloc_size, GFP_NOWAIT);
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while ((cn = of_find_node_by_type(cn, "cpu"))) {
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const u32 *rate, *reg;
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int len;
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if (cpu >= num_possible_cpus())
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break;
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for (cpu_eff = table_efficiency; cpu_eff->compatible; cpu_eff++)
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if (of_device_is_compatible(cn, cpu_eff->compatible))
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break;
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if (cpu_eff->compatible == NULL)
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continue;
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rate = of_get_property(cn, "clock-frequency", &len);
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if (!rate || len != 4) {
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pr_err("%s missing clock-frequency property\n",
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cn->full_name);
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continue;
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}
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reg = of_get_property(cn, "reg", &len);
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if (!reg || len != 4) {
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pr_err("%s missing reg property\n", cn->full_name);
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continue;
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}
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capacity = ((be32_to_cpup(rate)) >> 20) * cpu_eff->efficiency;
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/* Save min capacity of the system */
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if (capacity < min_capacity)
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min_capacity = capacity;
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/* Save max capacity of the system */
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if (capacity > max_capacity)
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max_capacity = capacity;
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cpu_capacity[cpu].capacity = capacity;
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cpu_capacity[cpu++].hwid = be32_to_cpup(reg);
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}
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if (cpu < num_possible_cpus())
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cpu_capacity[cpu].hwid = (unsigned long)(-1);
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/* If min and max capacities are equals, we bypass the update of the
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* cpu_scale because all CPUs have the same capacity. Otherwise, we
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* compute a middle_capacity factor that will ensure that the capacity
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* of an 'average' CPU of the system will be as close as possible to
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* SCHED_POWER_SCALE, which is the default value, but with the
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* constraint explained near table_efficiency[].
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*/
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if (min_capacity == max_capacity)
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cpu_capacity[0].hwid = (unsigned long)(-1);
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else if (4*max_capacity < (3*(max_capacity + min_capacity)))
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middle_capacity = (min_capacity + max_capacity)
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>> (SCHED_POWER_SHIFT+1);
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else
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middle_capacity = ((max_capacity / 3)
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>> (SCHED_POWER_SHIFT-1)) + 1;
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}
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/*
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* Look for a customed capacity of a CPU in the cpu_capacity table during the
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* boot. The update of all CPUs is in O(n^2) for heteregeneous system but the
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* function returns directly for SMP system.
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*/
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void update_cpu_power(unsigned int cpu, unsigned long hwid)
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{
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unsigned int idx = 0;
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/* look for the cpu's hwid in the cpu capacity table */
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for (idx = 0; idx < num_possible_cpus(); idx++) {
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if (cpu_capacity[idx].hwid == hwid)
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break;
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if (cpu_capacity[idx].hwid == -1)
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return;
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}
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if (idx == num_possible_cpus())
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return;
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set_power_scale(cpu, cpu_capacity[idx].capacity / middle_capacity);
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printk(KERN_INFO "CPU%u: update cpu_power %lu\n",
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cpu, arch_scale_freq_power(NULL, cpu));
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}
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#else
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static inline void parse_dt_topology(void) {}
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static inline void update_cpu_power(unsigned int cpuid, unsigned int mpidr) {}
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#endif
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/*
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* cpu topology table
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*/
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struct cputopo_arm cpu_topology[NR_CPUS];
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const struct cpumask *cpu_coregroup_mask(int cpu)
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{
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return &cpu_topology[cpu].core_sibling;
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}
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void update_siblings_masks(unsigned int cpuid)
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{
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struct cputopo_arm *cpu_topo, *cpuid_topo = &cpu_topology[cpuid];
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int cpu;
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/* update core and thread sibling masks */
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for_each_possible_cpu(cpu) {
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cpu_topo = &cpu_topology[cpu];
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if (cpuid_topo->socket_id != cpu_topo->socket_id)
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continue;
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cpumask_set_cpu(cpuid, &cpu_topo->core_sibling);
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if (cpu != cpuid)
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cpumask_set_cpu(cpu, &cpuid_topo->core_sibling);
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if (cpuid_topo->core_id != cpu_topo->core_id)
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continue;
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cpumask_set_cpu(cpuid, &cpu_topo->thread_sibling);
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if (cpu != cpuid)
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cpumask_set_cpu(cpu, &cpuid_topo->thread_sibling);
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}
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smp_wmb();
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}
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/*
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* store_cpu_topology is called at boot when only one cpu is running
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* and with the mutex cpu_hotplug.lock locked, when several cpus have booted,
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* which prevents simultaneous write access to cpu_topology array
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*/
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void store_cpu_topology(unsigned int cpuid)
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{
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struct cputopo_arm *cpuid_topo = &cpu_topology[cpuid];
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unsigned int mpidr;
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/* If the cpu topology has been already set, just return */
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if (cpuid_topo->core_id != -1)
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return;
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mpidr = read_cpuid_mpidr();
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/* create cpu topology mapping */
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if ((mpidr & MPIDR_SMP_BITMASK) == MPIDR_SMP_VALUE) {
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/*
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* This is a multiprocessor system
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* multiprocessor format & multiprocessor mode field are set
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*/
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if (mpidr & MPIDR_MT_BITMASK) {
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/* core performance interdependency */
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cpuid_topo->thread_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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cpuid_topo->socket_id = MPIDR_AFFINITY_LEVEL(mpidr, 2);
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} else {
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/* largely independent cores */
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cpuid_topo->thread_id = -1;
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cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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cpuid_topo->socket_id = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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}
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} else {
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/*
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* This is an uniprocessor system
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* we are in multiprocessor format but uniprocessor system
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* or in the old uniprocessor format
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*/
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cpuid_topo->thread_id = -1;
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cpuid_topo->core_id = 0;
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cpuid_topo->socket_id = -1;
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}
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update_siblings_masks(cpuid);
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update_cpu_power(cpuid, mpidr & MPIDR_HWID_BITMASK);
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printk(KERN_INFO "CPU%u: thread %d, cpu %d, socket %d, mpidr %x\n",
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cpuid, cpu_topology[cpuid].thread_id,
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cpu_topology[cpuid].core_id,
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cpu_topology[cpuid].socket_id, mpidr);
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}
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/*
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* init_cpu_topology is called at boot when only one cpu is running
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* which prevent simultaneous write access to cpu_topology array
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*/
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void __init init_cpu_topology(void)
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{
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unsigned int cpu;
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/* init core mask and power*/
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for_each_possible_cpu(cpu) {
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struct cputopo_arm *cpu_topo = &(cpu_topology[cpu]);
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cpu_topo->thread_id = -1;
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cpu_topo->core_id = -1;
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cpu_topo->socket_id = -1;
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cpumask_clear(&cpu_topo->core_sibling);
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cpumask_clear(&cpu_topo->thread_sibling);
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set_power_scale(cpu, SCHED_POWER_SCALE);
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}
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smp_wmb();
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parse_dt_topology();
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}
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