![Linus Torvalds](/assets/img/avatar_default.png)
The usual selection of bug fixes and driver updates for GPIO. Nothing really stands out except the addition of the GRGPIO driver and some enhacements to ACPI support -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABAgAGBQJRhuKVAAoJEEFnBt12D9kB8kUP/21N7fsCxNocqoIwX8VQPfEY KsXUKRstuETHERHpGCSvMuRAEy1vee9itijrmWOiQT09jztIxg3Sed3u0RCQjQEK mV87RdAObZzm6xTIpy5sQa1bMOlc2AzYhTDDr9f1OpU+L9XMhwq03wq/i74Zij3w 7vq5BkBfGWF84TY5ZG1SNIvtw9P2MYoCHtJKvFyTJWAH05m2bHSfuvvn8vIdcUBL TuVwoeUzbYJtTJatovkh0kyMOOZEh9JVWBPBTNNLyYDmpAKQ6RwBoAi0ZznmF4mk gp88dj6iMHebi7UnlDQJD5crw16cRoMh0pa3EBAjYM0IVhfn8AvFIhma34wTs1Z/ ZuWwwHeR93cQTKwMBT1OHRCPaOdjS5riAR4WJm5Tmq9dV0sjGlbwff26U1uHH8qX mTBA+tje4bVpSHEztmXyw0AOMUv2vid5P0F/sKtEHzfURf8Yjq8xvxyvq14T3dQQ /wzmdLKbzR05phft7Xxa4yzfSy46uvxyUJQQaKdU/jlay/gJFisJXJE0cOrwTOFo SpTCmjnacr8Tlqr04Fj8f8ZgOYrg5VAOUsVE8uY0ETWRCb7iezFw7JGE3qV1kZQk N1lPBbSnIwtkdMiEmyttxpFEb5PwJxX8pUP6JfNyMbMlHoZs2247SeakhRQs/OCx goJQEGz6eeOpvq7koiJg =PwUd -----END PGP SIGNATURE----- Merge tag 'gpio-for-linus' of git://git.secretlab.ca/git/linux Pull GPIO changes from Grant Likely: "The usual selection of bug fixes and driver updates for GPIO. Nothing really stands out except the addition of the GRGPIO driver and some enhacements to ACPI support" I'm pulling this despite the earlier mess. Let's hope it compiles these days. * tag 'gpio-for-linus' of git://git.secretlab.ca/git/linux: (46 commits) gpio: grgpio: Add irq support gpio: grgpio: Add device driver for GRGPIO cores gpiolib-acpi: introduce acpi_get_gpio_by_index() helper GPIO: gpio-generic: remove kfree() from bgpio_remove call gpio / ACPI: Handle ACPI events in accordance with the spec gpio: lpc32xx: Fix off-by-one valid range checking for bank gpio: mcp23s08: convert driver to DT gpio/omap: force restore if context loss is not detectable gpio/omap: optimise interrupt service routine gpio/omap: remove extra context restores in *_runtime_resume() gpio/omap: free irq domain in probe() failure paths gpio: gpio-generic: Add 16 and 32 bit big endian byte order support gpio: samsung: Add terminating entry for exynos_pinctrl_ids gpio: mvebu: add dbg_show function MAX7301 GPIO: Do not force SPI speed when using OF Platform gpio: gpio-tps65910.c: fix checkpatch error gpio: gpio-timberdale.c: fix checkpatch error gpio: gpio-tc3589x.c: fix checkpatch errors gpio: gpio-stp-xway.c: fix checkpatch error gpio: gpio-sch.c: fix checkpatch error ...
576 lines
14 KiB
C
576 lines
14 KiB
C
/*
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* arch/arm/mach-tegra/gpio.c
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*
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* Copyright (c) 2010 Google, Inc
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*
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* Author:
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* Erik Gilling <konkers@google.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/module.h>
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#include <linux/irqdomain.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/pm.h>
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#define GPIO_BANK(x) ((x) >> 5)
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#define GPIO_PORT(x) (((x) >> 3) & 0x3)
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#define GPIO_BIT(x) ((x) & 0x7)
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#define GPIO_REG(x) (GPIO_BANK(x) * tegra_gpio_bank_stride + \
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GPIO_PORT(x) * 4)
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#define GPIO_CNF(x) (GPIO_REG(x) + 0x00)
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#define GPIO_OE(x) (GPIO_REG(x) + 0x10)
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#define GPIO_OUT(x) (GPIO_REG(x) + 0X20)
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#define GPIO_IN(x) (GPIO_REG(x) + 0x30)
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#define GPIO_INT_STA(x) (GPIO_REG(x) + 0x40)
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#define GPIO_INT_ENB(x) (GPIO_REG(x) + 0x50)
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#define GPIO_INT_LVL(x) (GPIO_REG(x) + 0x60)
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#define GPIO_INT_CLR(x) (GPIO_REG(x) + 0x70)
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#define GPIO_MSK_CNF(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x00)
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#define GPIO_MSK_OE(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x10)
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#define GPIO_MSK_OUT(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0X20)
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#define GPIO_MSK_INT_STA(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x40)
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#define GPIO_MSK_INT_ENB(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x50)
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#define GPIO_MSK_INT_LVL(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x60)
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#define GPIO_INT_LVL_MASK 0x010101
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#define GPIO_INT_LVL_EDGE_RISING 0x000101
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#define GPIO_INT_LVL_EDGE_FALLING 0x000100
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#define GPIO_INT_LVL_EDGE_BOTH 0x010100
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#define GPIO_INT_LVL_LEVEL_HIGH 0x000001
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#define GPIO_INT_LVL_LEVEL_LOW 0x000000
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struct tegra_gpio_bank {
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int bank;
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int irq;
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spinlock_t lvl_lock[4];
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#ifdef CONFIG_PM_SLEEP
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u32 cnf[4];
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u32 out[4];
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u32 oe[4];
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u32 int_enb[4];
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u32 int_lvl[4];
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u32 wake_enb[4];
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#endif
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};
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static struct irq_domain *irq_domain;
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static void __iomem *regs;
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static u32 tegra_gpio_bank_count;
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static u32 tegra_gpio_bank_stride;
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static u32 tegra_gpio_upper_offset;
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static struct tegra_gpio_bank *tegra_gpio_banks;
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static inline void tegra_gpio_writel(u32 val, u32 reg)
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{
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__raw_writel(val, regs + reg);
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}
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static inline u32 tegra_gpio_readl(u32 reg)
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{
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return __raw_readl(regs + reg);
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}
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static int tegra_gpio_compose(int bank, int port, int bit)
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{
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return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
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}
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static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
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{
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u32 val;
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val = 0x100 << GPIO_BIT(gpio);
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if (value)
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val |= 1 << GPIO_BIT(gpio);
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tegra_gpio_writel(val, reg);
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}
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static void tegra_gpio_enable(int gpio)
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{
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tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
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}
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static void tegra_gpio_disable(int gpio)
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{
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tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
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}
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static int tegra_gpio_request(struct gpio_chip *chip, unsigned offset)
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{
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return pinctrl_request_gpio(offset);
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}
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static void tegra_gpio_free(struct gpio_chip *chip, unsigned offset)
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{
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pinctrl_free_gpio(offset);
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tegra_gpio_disable(offset);
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}
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static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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{
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tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value);
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}
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static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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/* If gpio is in output mode then read from the out value */
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if ((tegra_gpio_readl(GPIO_OE(offset)) >> GPIO_BIT(offset)) & 1)
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return (tegra_gpio_readl(GPIO_OUT(offset)) >>
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GPIO_BIT(offset)) & 0x1;
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return (tegra_gpio_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1;
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}
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static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
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tegra_gpio_enable(offset);
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return 0;
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}
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static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
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int value)
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{
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tegra_gpio_set(chip, offset, value);
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tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
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tegra_gpio_enable(offset);
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return 0;
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}
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static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
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{
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return irq_find_mapping(irq_domain, offset);
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}
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static struct gpio_chip tegra_gpio_chip = {
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.label = "tegra-gpio",
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.request = tegra_gpio_request,
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.free = tegra_gpio_free,
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.direction_input = tegra_gpio_direction_input,
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.get = tegra_gpio_get,
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.direction_output = tegra_gpio_direction_output,
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.set = tegra_gpio_set,
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.to_irq = tegra_gpio_to_irq,
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.base = 0,
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};
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static void tegra_gpio_irq_ack(struct irq_data *d)
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{
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int gpio = d->hwirq;
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tegra_gpio_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio));
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}
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static void tegra_gpio_irq_mask(struct irq_data *d)
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{
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int gpio = d->hwirq;
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tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0);
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}
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static void tegra_gpio_irq_unmask(struct irq_data *d)
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{
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int gpio = d->hwirq;
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tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1);
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}
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static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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{
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int gpio = d->hwirq;
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struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
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int port = GPIO_PORT(gpio);
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int lvl_type;
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int val;
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unsigned long flags;
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switch (type & IRQ_TYPE_SENSE_MASK) {
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case IRQ_TYPE_EDGE_RISING:
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lvl_type = GPIO_INT_LVL_EDGE_RISING;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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lvl_type = GPIO_INT_LVL_EDGE_FALLING;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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lvl_type = GPIO_INT_LVL_EDGE_BOTH;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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lvl_type = GPIO_INT_LVL_LEVEL_LOW;
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break;
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default:
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return -EINVAL;
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}
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spin_lock_irqsave(&bank->lvl_lock[port], flags);
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val = tegra_gpio_readl(GPIO_INT_LVL(gpio));
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val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
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val |= lvl_type << GPIO_BIT(gpio);
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tegra_gpio_writel(val, GPIO_INT_LVL(gpio));
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spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
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tegra_gpio_mask_write(GPIO_MSK_OE(gpio), gpio, 0);
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tegra_gpio_enable(gpio);
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if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
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__irq_set_handler_locked(d->irq, handle_level_irq);
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else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
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__irq_set_handler_locked(d->irq, handle_edge_irq);
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return 0;
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}
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static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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struct tegra_gpio_bank *bank;
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int port;
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int pin;
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int unmasked = 0;
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struct irq_chip *chip = irq_desc_get_chip(desc);
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chained_irq_enter(chip, desc);
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bank = irq_get_handler_data(irq);
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for (port = 0; port < 4; port++) {
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int gpio = tegra_gpio_compose(bank->bank, port, 0);
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unsigned long sta = tegra_gpio_readl(GPIO_INT_STA(gpio)) &
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tegra_gpio_readl(GPIO_INT_ENB(gpio));
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u32 lvl = tegra_gpio_readl(GPIO_INT_LVL(gpio));
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for_each_set_bit(pin, &sta, 8) {
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tegra_gpio_writel(1 << pin, GPIO_INT_CLR(gpio));
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/* if gpio is edge triggered, clear condition
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* before executing the hander so that we don't
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* miss edges
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*/
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if (lvl & (0x100 << pin)) {
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unmasked = 1;
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chained_irq_exit(chip, desc);
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}
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generic_handle_irq(gpio_to_irq(gpio + pin));
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}
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}
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if (!unmasked)
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chained_irq_exit(chip, desc);
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}
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#ifdef CONFIG_PM_SLEEP
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static int tegra_gpio_resume(struct device *dev)
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{
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unsigned long flags;
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int b;
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int p;
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local_irq_save(flags);
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for (b = 0; b < tegra_gpio_bank_count; b++) {
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struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
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for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
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unsigned int gpio = (b<<5) | (p<<3);
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tegra_gpio_writel(bank->cnf[p], GPIO_CNF(gpio));
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tegra_gpio_writel(bank->out[p], GPIO_OUT(gpio));
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tegra_gpio_writel(bank->oe[p], GPIO_OE(gpio));
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tegra_gpio_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio));
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tegra_gpio_writel(bank->int_enb[p], GPIO_INT_ENB(gpio));
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}
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}
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local_irq_restore(flags);
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return 0;
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}
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static int tegra_gpio_suspend(struct device *dev)
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{
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unsigned long flags;
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int b;
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int p;
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local_irq_save(flags);
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for (b = 0; b < tegra_gpio_bank_count; b++) {
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struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
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for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
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unsigned int gpio = (b<<5) | (p<<3);
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bank->cnf[p] = tegra_gpio_readl(GPIO_CNF(gpio));
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bank->out[p] = tegra_gpio_readl(GPIO_OUT(gpio));
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bank->oe[p] = tegra_gpio_readl(GPIO_OE(gpio));
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bank->int_enb[p] = tegra_gpio_readl(GPIO_INT_ENB(gpio));
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bank->int_lvl[p] = tegra_gpio_readl(GPIO_INT_LVL(gpio));
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/* Enable gpio irq for wake up source */
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tegra_gpio_writel(bank->wake_enb[p],
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GPIO_INT_ENB(gpio));
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}
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}
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local_irq_restore(flags);
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return 0;
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}
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static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
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{
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struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
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int gpio = d->hwirq;
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u32 port, bit, mask;
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port = GPIO_PORT(gpio);
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bit = GPIO_BIT(gpio);
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mask = BIT(bit);
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if (enable)
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bank->wake_enb[port] |= mask;
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else
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bank->wake_enb[port] &= ~mask;
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return irq_set_irq_wake(bank->irq, enable);
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}
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#endif
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static struct irq_chip tegra_gpio_irq_chip = {
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.name = "GPIO",
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.irq_ack = tegra_gpio_irq_ack,
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.irq_mask = tegra_gpio_irq_mask,
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.irq_unmask = tegra_gpio_irq_unmask,
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.irq_set_type = tegra_gpio_irq_set_type,
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#ifdef CONFIG_PM_SLEEP
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.irq_set_wake = tegra_gpio_irq_set_wake,
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#endif
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};
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static const struct dev_pm_ops tegra_gpio_pm_ops = {
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SET_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume)
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};
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struct tegra_gpio_soc_config {
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u32 bank_stride;
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u32 upper_offset;
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};
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static struct tegra_gpio_soc_config tegra20_gpio_config = {
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.bank_stride = 0x80,
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.upper_offset = 0x800,
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};
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static struct tegra_gpio_soc_config tegra30_gpio_config = {
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.bank_stride = 0x100,
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.upper_offset = 0x80,
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};
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static struct of_device_id tegra_gpio_of_match[] = {
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{ .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config },
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{ .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config },
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{ },
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};
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/* This lock class tells lockdep that GPIO irqs are in a different
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* category than their parents, so it won't report false recursion.
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*/
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static struct lock_class_key gpio_lock_class;
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static int tegra_gpio_probe(struct platform_device *pdev)
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{
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const struct of_device_id *match;
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struct tegra_gpio_soc_config *config;
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struct resource *res;
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struct tegra_gpio_bank *bank;
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int gpio;
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int i;
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int j;
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match = of_match_device(tegra_gpio_of_match, &pdev->dev);
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if (!match) {
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dev_err(&pdev->dev, "Error: No device match found\n");
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return -ENODEV;
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}
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config = (struct tegra_gpio_soc_config *)match->data;
|
|
|
|
tegra_gpio_bank_stride = config->bank_stride;
|
|
tegra_gpio_upper_offset = config->upper_offset;
|
|
|
|
for (;;) {
|
|
res = platform_get_resource(pdev, IORESOURCE_IRQ, tegra_gpio_bank_count);
|
|
if (!res)
|
|
break;
|
|
tegra_gpio_bank_count++;
|
|
}
|
|
if (!tegra_gpio_bank_count) {
|
|
dev_err(&pdev->dev, "Missing IRQ resource\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
tegra_gpio_chip.ngpio = tegra_gpio_bank_count * 32;
|
|
|
|
tegra_gpio_banks = devm_kzalloc(&pdev->dev,
|
|
tegra_gpio_bank_count * sizeof(*tegra_gpio_banks),
|
|
GFP_KERNEL);
|
|
if (!tegra_gpio_banks) {
|
|
dev_err(&pdev->dev, "Couldn't allocate bank structure\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
irq_domain = irq_domain_add_linear(pdev->dev.of_node,
|
|
tegra_gpio_chip.ngpio,
|
|
&irq_domain_simple_ops, NULL);
|
|
if (!irq_domain)
|
|
return -ENODEV;
|
|
|
|
for (i = 0; i < tegra_gpio_bank_count; i++) {
|
|
res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
|
|
if (!res) {
|
|
dev_err(&pdev->dev, "Missing IRQ resource\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
bank = &tegra_gpio_banks[i];
|
|
bank->bank = i;
|
|
bank->irq = res->start;
|
|
}
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!res) {
|
|
dev_err(&pdev->dev, "Missing MEM resource\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
regs = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(regs))
|
|
return PTR_ERR(regs);
|
|
|
|
for (i = 0; i < tegra_gpio_bank_count; i++) {
|
|
for (j = 0; j < 4; j++) {
|
|
int gpio = tegra_gpio_compose(i, j, 0);
|
|
tegra_gpio_writel(0x00, GPIO_INT_ENB(gpio));
|
|
}
|
|
}
|
|
|
|
tegra_gpio_chip.of_node = pdev->dev.of_node;
|
|
|
|
gpiochip_add(&tegra_gpio_chip);
|
|
|
|
for (gpio = 0; gpio < tegra_gpio_chip.ngpio; gpio++) {
|
|
int irq = irq_create_mapping(irq_domain, gpio);
|
|
/* No validity check; all Tegra GPIOs are valid IRQs */
|
|
|
|
bank = &tegra_gpio_banks[GPIO_BANK(gpio)];
|
|
|
|
irq_set_lockdep_class(irq, &gpio_lock_class);
|
|
irq_set_chip_data(irq, bank);
|
|
irq_set_chip_and_handler(irq, &tegra_gpio_irq_chip,
|
|
handle_simple_irq);
|
|
set_irq_flags(irq, IRQF_VALID);
|
|
}
|
|
|
|
for (i = 0; i < tegra_gpio_bank_count; i++) {
|
|
bank = &tegra_gpio_banks[i];
|
|
|
|
irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler);
|
|
irq_set_handler_data(bank->irq, bank);
|
|
|
|
for (j = 0; j < 4; j++)
|
|
spin_lock_init(&bank->lvl_lock[j]);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver tegra_gpio_driver = {
|
|
.driver = {
|
|
.name = "tegra-gpio",
|
|
.owner = THIS_MODULE,
|
|
.pm = &tegra_gpio_pm_ops,
|
|
.of_match_table = tegra_gpio_of_match,
|
|
},
|
|
.probe = tegra_gpio_probe,
|
|
};
|
|
|
|
static int __init tegra_gpio_init(void)
|
|
{
|
|
return platform_driver_register(&tegra_gpio_driver);
|
|
}
|
|
postcore_initcall(tegra_gpio_init);
|
|
|
|
#ifdef CONFIG_DEBUG_FS
|
|
|
|
#include <linux/debugfs.h>
|
|
#include <linux/seq_file.h>
|
|
|
|
static int dbg_gpio_show(struct seq_file *s, void *unused)
|
|
{
|
|
int i;
|
|
int j;
|
|
|
|
for (i = 0; i < tegra_gpio_bank_count; i++) {
|
|
for (j = 0; j < 4; j++) {
|
|
int gpio = tegra_gpio_compose(i, j, 0);
|
|
seq_printf(s,
|
|
"%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
|
|
i, j,
|
|
tegra_gpio_readl(GPIO_CNF(gpio)),
|
|
tegra_gpio_readl(GPIO_OE(gpio)),
|
|
tegra_gpio_readl(GPIO_OUT(gpio)),
|
|
tegra_gpio_readl(GPIO_IN(gpio)),
|
|
tegra_gpio_readl(GPIO_INT_STA(gpio)),
|
|
tegra_gpio_readl(GPIO_INT_ENB(gpio)),
|
|
tegra_gpio_readl(GPIO_INT_LVL(gpio)));
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int dbg_gpio_open(struct inode *inode, struct file *file)
|
|
{
|
|
return single_open(file, dbg_gpio_show, &inode->i_private);
|
|
}
|
|
|
|
static const struct file_operations debug_fops = {
|
|
.open = dbg_gpio_open,
|
|
.read = seq_read,
|
|
.llseek = seq_lseek,
|
|
.release = single_release,
|
|
};
|
|
|
|
static int __init tegra_gpio_debuginit(void)
|
|
{
|
|
(void) debugfs_create_file("tegra_gpio", S_IRUGO,
|
|
NULL, NULL, &debug_fops);
|
|
return 0;
|
|
}
|
|
late_initcall(tegra_gpio_debuginit);
|
|
#endif
|