501 lines
12 KiB
C
501 lines
12 KiB
C
/*
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* Implement the default iomap interfaces
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*
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* (C) Copyright 2004 Linus Torvalds
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*/
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#include <linux/pci.h>
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#include <linux/io.h>
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#ifdef CONFIG_GENERIC_IOMAP
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#include <linux/module.h>
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/*
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* Read/write from/to an (offsettable) iomem cookie. It might be a PIO
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* access or a MMIO access, these functions don't care. The info is
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* encoded in the hardware mapping set up by the mapping functions
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* (or the cookie itself, depending on implementation and hw).
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*
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* The generic routines don't assume any hardware mappings, and just
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* encode the PIO/MMIO as part of the cookie. They coldly assume that
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* the MMIO IO mappings are not in the low address range.
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*
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* Architectures for which this is not true can't use this generic
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* implementation and should do their own copy.
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*/
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#ifndef HAVE_ARCH_PIO_SIZE
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/*
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* We encode the physical PIO addresses (0-0xffff) into the
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* pointer by offsetting them with a constant (0x10000) and
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* assuming that all the low addresses are always PIO. That means
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* we can do some sanity checks on the low bits, and don't
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* need to just take things for granted.
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*/
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#define PIO_OFFSET 0x10000UL
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#define PIO_MASK 0x0ffffUL
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#define PIO_RESERVED 0x40000UL
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#endif
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/*
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* Ugly macros are a way of life.
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*/
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#define VERIFY_PIO(port) BUG_ON((port & ~PIO_MASK) != PIO_OFFSET)
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#define IO_COND(addr, is_pio, is_mmio) do { \
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unsigned long port = (unsigned long __force)addr; \
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if (port < PIO_RESERVED) { \
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VERIFY_PIO(port); \
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port &= PIO_MASK; \
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is_pio; \
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} else { \
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is_mmio; \
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} \
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} while (0)
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#ifndef pio_read16be
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#define pio_read16be(port) swab16(inw(port))
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#define pio_read32be(port) swab32(inl(port))
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#endif
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#ifndef mmio_read16be
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#define mmio_read16be(addr) be16_to_cpu(__raw_readw(addr))
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#define mmio_read32be(addr) be32_to_cpu(__raw_readl(addr))
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#endif
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unsigned int fastcall ioread8(void __iomem *addr)
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{
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IO_COND(addr, return inb(port), return readb(addr));
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}
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unsigned int fastcall ioread16(void __iomem *addr)
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{
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IO_COND(addr, return inw(port), return readw(addr));
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}
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unsigned int fastcall ioread16be(void __iomem *addr)
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{
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IO_COND(addr, return pio_read16be(port), return mmio_read16be(addr));
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}
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unsigned int fastcall ioread32(void __iomem *addr)
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{
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IO_COND(addr, return inl(port), return readl(addr));
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}
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unsigned int fastcall ioread32be(void __iomem *addr)
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{
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IO_COND(addr, return pio_read32be(port), return mmio_read32be(addr));
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}
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EXPORT_SYMBOL(ioread8);
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EXPORT_SYMBOL(ioread16);
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EXPORT_SYMBOL(ioread16be);
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EXPORT_SYMBOL(ioread32);
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EXPORT_SYMBOL(ioread32be);
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#ifndef pio_write16be
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#define pio_write16be(val,port) outw(swab16(val),port)
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#define pio_write32be(val,port) outl(swab32(val),port)
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#endif
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#ifndef mmio_write16be
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#define mmio_write16be(val,port) __raw_writew(be16_to_cpu(val),port)
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#define mmio_write32be(val,port) __raw_writel(be32_to_cpu(val),port)
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#endif
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void fastcall iowrite8(u8 val, void __iomem *addr)
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{
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IO_COND(addr, outb(val,port), writeb(val, addr));
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}
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void fastcall iowrite16(u16 val, void __iomem *addr)
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{
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IO_COND(addr, outw(val,port), writew(val, addr));
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}
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void fastcall iowrite16be(u16 val, void __iomem *addr)
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{
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IO_COND(addr, pio_write16be(val,port), mmio_write16be(val, addr));
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}
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void fastcall iowrite32(u32 val, void __iomem *addr)
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{
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IO_COND(addr, outl(val,port), writel(val, addr));
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}
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void fastcall iowrite32be(u32 val, void __iomem *addr)
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{
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IO_COND(addr, pio_write32be(val,port), mmio_write32be(val, addr));
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}
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EXPORT_SYMBOL(iowrite8);
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EXPORT_SYMBOL(iowrite16);
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EXPORT_SYMBOL(iowrite16be);
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EXPORT_SYMBOL(iowrite32);
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EXPORT_SYMBOL(iowrite32be);
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/*
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* These are the "repeat MMIO read/write" functions.
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* Note the "__raw" accesses, since we don't want to
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* convert to CPU byte order. We write in "IO byte
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* order" (we also don't have IO barriers).
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*/
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#ifndef mmio_insb
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static inline void mmio_insb(void __iomem *addr, u8 *dst, int count)
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{
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while (--count >= 0) {
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u8 data = __raw_readb(addr);
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*dst = data;
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dst++;
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}
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}
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static inline void mmio_insw(void __iomem *addr, u16 *dst, int count)
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{
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while (--count >= 0) {
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u16 data = __raw_readw(addr);
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*dst = data;
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dst++;
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}
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}
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static inline void mmio_insl(void __iomem *addr, u32 *dst, int count)
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{
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while (--count >= 0) {
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u32 data = __raw_readl(addr);
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*dst = data;
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dst++;
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}
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}
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#endif
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#ifndef mmio_outsb
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static inline void mmio_outsb(void __iomem *addr, const u8 *src, int count)
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{
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while (--count >= 0) {
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__raw_writeb(*src, addr);
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src++;
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}
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}
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static inline void mmio_outsw(void __iomem *addr, const u16 *src, int count)
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{
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while (--count >= 0) {
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__raw_writew(*src, addr);
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src++;
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}
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}
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static inline void mmio_outsl(void __iomem *addr, const u32 *src, int count)
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{
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while (--count >= 0) {
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__raw_writel(*src, addr);
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src++;
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}
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}
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#endif
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void fastcall ioread8_rep(void __iomem *addr, void *dst, unsigned long count)
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{
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IO_COND(addr, insb(port,dst,count), mmio_insb(addr, dst, count));
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}
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void fastcall ioread16_rep(void __iomem *addr, void *dst, unsigned long count)
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{
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IO_COND(addr, insw(port,dst,count), mmio_insw(addr, dst, count));
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}
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void fastcall ioread32_rep(void __iomem *addr, void *dst, unsigned long count)
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{
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IO_COND(addr, insl(port,dst,count), mmio_insl(addr, dst, count));
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}
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EXPORT_SYMBOL(ioread8_rep);
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EXPORT_SYMBOL(ioread16_rep);
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EXPORT_SYMBOL(ioread32_rep);
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void fastcall iowrite8_rep(void __iomem *addr, const void *src, unsigned long count)
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{
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IO_COND(addr, outsb(port, src, count), mmio_outsb(addr, src, count));
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}
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void fastcall iowrite16_rep(void __iomem *addr, const void *src, unsigned long count)
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{
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IO_COND(addr, outsw(port, src, count), mmio_outsw(addr, src, count));
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}
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void fastcall iowrite32_rep(void __iomem *addr, const void *src, unsigned long count)
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{
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IO_COND(addr, outsl(port, src,count), mmio_outsl(addr, src, count));
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}
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EXPORT_SYMBOL(iowrite8_rep);
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EXPORT_SYMBOL(iowrite16_rep);
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EXPORT_SYMBOL(iowrite32_rep);
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/* Create a virtual mapping cookie for an IO port range */
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void __iomem *ioport_map(unsigned long port, unsigned int nr)
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{
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if (port > PIO_MASK)
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return NULL;
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return (void __iomem *) (unsigned long) (port + PIO_OFFSET);
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}
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void ioport_unmap(void __iomem *addr)
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{
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/* Nothing to do */
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}
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EXPORT_SYMBOL(ioport_map);
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EXPORT_SYMBOL(ioport_unmap);
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/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
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void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
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{
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unsigned long start = pci_resource_start(dev, bar);
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unsigned long len = pci_resource_len(dev, bar);
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unsigned long flags = pci_resource_flags(dev, bar);
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if (!len || !start)
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return NULL;
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if (maxlen && len > maxlen)
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len = maxlen;
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if (flags & IORESOURCE_IO)
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return ioport_map(start, len);
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if (flags & IORESOURCE_MEM) {
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if (flags & IORESOURCE_CACHEABLE)
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return ioremap(start, len);
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return ioremap_nocache(start, len);
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}
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/* What? */
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return NULL;
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}
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void pci_iounmap(struct pci_dev *dev, void __iomem * addr)
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{
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IO_COND(addr, /* nothing */, iounmap(addr));
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}
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EXPORT_SYMBOL(pci_iomap);
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EXPORT_SYMBOL(pci_iounmap);
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#endif /* CONFIG_GENERIC_IOMAP */
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/*
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* Generic iomap devres
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*/
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static void devm_ioport_map_release(struct device *dev, void *res)
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{
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ioport_unmap(*(void __iomem **)res);
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}
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static int devm_ioport_map_match(struct device *dev, void *res,
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void *match_data)
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{
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return *(void **)res == match_data;
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}
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/**
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* devm_ioport_map - Managed ioport_map()
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* @dev: Generic device to map ioport for
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* @port: Port to map
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* @nr: Number of ports to map
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*
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* Managed ioport_map(). Map is automatically unmapped on driver
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* detach.
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*/
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void __iomem * devm_ioport_map(struct device *dev, unsigned long port,
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unsigned int nr)
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{
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void __iomem **ptr, *addr;
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ptr = devres_alloc(devm_ioport_map_release, sizeof(*ptr), GFP_KERNEL);
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if (!ptr)
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return NULL;
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addr = ioport_map(port, nr);
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if (addr) {
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*ptr = addr;
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devres_add(dev, ptr);
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} else
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devres_free(ptr);
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return addr;
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}
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EXPORT_SYMBOL(devm_ioport_map);
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/**
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* devm_ioport_unmap - Managed ioport_unmap()
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* @dev: Generic device to unmap for
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* @addr: Address to unmap
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*
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* Managed ioport_unmap(). @addr must have been mapped using
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* devm_ioport_map().
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*/
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void devm_ioport_unmap(struct device *dev, void __iomem *addr)
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{
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ioport_unmap(addr);
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WARN_ON(devres_destroy(dev, devm_ioport_map_release,
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devm_ioport_map_match, (void *)addr));
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}
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EXPORT_SYMBOL(devm_ioport_unmap);
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static void devm_ioremap_release(struct device *dev, void *res)
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{
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iounmap(*(void __iomem **)res);
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}
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static int devm_ioremap_match(struct device *dev, void *res, void *match_data)
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{
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return *(void **)res == match_data;
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}
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/**
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* devm_ioremap - Managed ioremap()
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* @dev: Generic device to remap IO address for
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* @offset: BUS offset to map
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* @size: Size of map
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*
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* Managed ioremap(). Map is automatically unmapped on driver detach.
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*/
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void __iomem *devm_ioremap(struct device *dev, unsigned long offset,
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unsigned long size)
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{
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void __iomem **ptr, *addr;
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ptr = devres_alloc(devm_ioremap_release, sizeof(*ptr), GFP_KERNEL);
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if (!ptr)
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return NULL;
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addr = ioremap(offset, size);
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if (addr) {
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*ptr = addr;
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devres_add(dev, ptr);
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} else
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devres_free(ptr);
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return addr;
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}
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EXPORT_SYMBOL(devm_ioremap);
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/**
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* devm_ioremap_nocache - Managed ioremap_nocache()
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* @dev: Generic device to remap IO address for
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* @offset: BUS offset to map
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* @size: Size of map
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*
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* Managed ioremap_nocache(). Map is automatically unmapped on driver
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* detach.
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*/
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void __iomem *devm_ioremap_nocache(struct device *dev, unsigned long offset,
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unsigned long size)
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{
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void __iomem **ptr, *addr;
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ptr = devres_alloc(devm_ioremap_release, sizeof(*ptr), GFP_KERNEL);
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if (!ptr)
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return NULL;
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addr = ioremap_nocache(offset, size);
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if (addr) {
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*ptr = addr;
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devres_add(dev, ptr);
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} else
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devres_free(ptr);
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return addr;
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}
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EXPORT_SYMBOL(devm_ioremap_nocache);
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/**
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* devm_iounmap - Managed iounmap()
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* @dev: Generic device to unmap for
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* @addr: Address to unmap
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*
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* Managed iounmap(). @addr must have been mapped using devm_ioremap*().
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*/
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void devm_iounmap(struct device *dev, void __iomem *addr)
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{
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iounmap(addr);
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WARN_ON(devres_destroy(dev, devm_ioremap_release, devm_ioremap_match,
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(void *)addr));
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}
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EXPORT_SYMBOL(devm_iounmap);
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/*
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* PCI iomap devres
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*/
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#define PCIM_IOMAP_MAX PCI_ROM_RESOURCE
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struct pcim_iomap_devres {
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void __iomem *table[PCIM_IOMAP_MAX];
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};
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static void pcim_iomap_release(struct device *gendev, void *res)
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{
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struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
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struct pcim_iomap_devres *this = res;
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int i;
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for (i = 0; i < PCIM_IOMAP_MAX; i++)
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if (this->table[i])
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pci_iounmap(dev, this->table[i]);
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}
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/**
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* pcim_iomap_table - access iomap allocation table
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* @pdev: PCI device to access iomap table for
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*
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* Access iomap allocation table for @dev. If iomap table doesn't
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* exist and @pdev is managed, it will be allocated. All iomaps
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* recorded in the iomap table are automatically unmapped on driver
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* detach.
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*
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* This function might sleep when the table is first allocated but can
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* be safely called without context and guaranteed to succed once
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* allocated.
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*/
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void __iomem * const * pcim_iomap_table(struct pci_dev *pdev)
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{
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struct pcim_iomap_devres *dr, *new_dr;
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dr = devres_find(&pdev->dev, pcim_iomap_release, NULL, NULL);
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if (dr)
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return dr->table;
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new_dr = devres_alloc(pcim_iomap_release, sizeof(*new_dr), GFP_KERNEL);
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if (!new_dr)
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return NULL;
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dr = devres_get(&pdev->dev, new_dr, NULL, NULL);
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return dr->table;
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}
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EXPORT_SYMBOL(pcim_iomap_table);
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/**
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* pcim_iomap - Managed pcim_iomap()
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* @pdev: PCI device to iomap for
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* @bar: BAR to iomap
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* @maxlen: Maximum length of iomap
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*
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* Managed pci_iomap(). Map is automatically unmapped on driver
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* detach.
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*/
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void __iomem * pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen)
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{
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void __iomem **tbl;
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BUG_ON(bar >= PCIM_IOMAP_MAX);
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tbl = (void __iomem **)pcim_iomap_table(pdev);
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if (!tbl || tbl[bar]) /* duplicate mappings not allowed */
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return NULL;
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tbl[bar] = pci_iomap(pdev, bar, maxlen);
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return tbl[bar];
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}
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EXPORT_SYMBOL(pcim_iomap);
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/**
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* pcim_iounmap - Managed pci_iounmap()
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* @pdev: PCI device to iounmap for
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* @addr: Address to unmap
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*
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* Managed pci_iounmap(). @addr must have been mapped using pcim_iomap().
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*/
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void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr)
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{
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void __iomem **tbl;
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int i;
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pci_iounmap(pdev, addr);
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tbl = (void __iomem **)pcim_iomap_table(pdev);
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BUG_ON(!tbl);
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for (i = 0; i < PCIM_IOMAP_MAX; i++)
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if (tbl[i] == addr) {
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tbl[i] = NULL;
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return;
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}
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WARN_ON(1);
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}
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EXPORT_SYMBOL(pcim_iounmap);
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