52c543f90c
This patch adds the foundation pieces for the Freescale MXC platforms, including i.MX2 and i.MX3 based systems. The bare-bones MX31 support in this patch boots to the rootdev panic with 8250 serial console configured "console=ttyS0,115200". It assumes that Redboot is the boot loader. Signed-off-by: Quinn Jensen <quinn.jensen@freescale.com> Acked-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
84 lines
1.9 KiB
C
84 lines
1.9 KiB
C
/*
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* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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*/
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/init.h>
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#include <linux/device.h>
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#include <linux/errno.h>
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#include <asm/hardware.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/mach/irq.h>
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#include <asm/arch/common.h>
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/*!
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* Disable interrupt number "irq" in the AVIC
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*
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* @param irq interrupt source number
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*/
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static void mxc_mask_irq(unsigned int irq)
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{
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__raw_writel(irq, AVIC_INTDISNUM);
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}
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/*!
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* Enable interrupt number "irq" in the AVIC
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*
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* @param irq interrupt source number
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*/
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static void mxc_unmask_irq(unsigned int irq)
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{
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__raw_writel(irq, AVIC_INTENNUM);
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}
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static struct irq_chip mxc_avic_chip = {
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.mask_ack = mxc_mask_irq,
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.mask = mxc_mask_irq,
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.unmask = mxc_unmask_irq,
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};
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/*!
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* This function initializes the AVIC hardware and disables all the
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* interrupts. It registers the interrupt enable and disable functions
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* to the kernel for each interrupt source.
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*/
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void __init mxc_init_irq(void)
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{
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int i;
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u32 reg;
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/* put the AVIC into the reset value with
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* all interrupts disabled
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*/
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__raw_writel(0, AVIC_INTCNTL);
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__raw_writel(0x1f, AVIC_NIMASK);
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/* disable all interrupts */
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__raw_writel(0, AVIC_INTENABLEH);
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__raw_writel(0, AVIC_INTENABLEL);
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/* all IRQ no FIQ */
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__raw_writel(0, AVIC_INTTYPEH);
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__raw_writel(0, AVIC_INTTYPEL);
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for (i = 0; i < MXC_MAX_INT_LINES; i++) {
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set_irq_chip(i, &mxc_avic_chip);
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set_irq_handler(i, handle_level_irq);
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set_irq_flags(i, IRQF_VALID);
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}
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/* Set WDOG2's interrupt the highest priority level (bit 28-31) */
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reg = __raw_readl(AVIC_NIPRIORITY6);
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reg |= (0xF << 28);
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__raw_writel(reg, AVIC_NIPRIORITY6);
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printk(KERN_INFO "MXC IRQ initialized\n");
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}
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