136819a6e8
Realtek PHYs implement the concept of so-called "extension pages". The reason for this is probably because these PHYs expose more registers than available in the standard address range. After all read/write operations on such a page are done the driver should switch back to page 0 where the standard MII registers (such as MII_BMCR) are available. When referring to such a register the datasheets of RTL8211E and RTL8211F always specify: - the page / "ext. page" which has to be written to RTL821x_PAGE_SELECT - an address (sometimes also called reg) These new utility functions make the existing code easier to read since it removes some duplication (switching back to page 0 is done within the new helpers for example). No functional changes are intended. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
254 lines
5.6 KiB
C
254 lines
5.6 KiB
C
/*
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* drivers/net/phy/realtek.c
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*
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* Driver for Realtek PHYs
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*
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* Author: Johnson Leung <r58129@freescale.com>
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*
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* Copyright (c) 2004 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#include <linux/bitops.h>
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#include <linux/phy.h>
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#include <linux/module.h>
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#define RTL821x_PHYSR 0x11
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#define RTL821x_PHYSR_DUPLEX BIT(13)
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#define RTL821x_PHYSR_SPEED GENMASK(15, 14)
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#define RTL821x_INER 0x12
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#define RTL8211B_INER_INIT 0x6400
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#define RTL8211E_INER_LINK_STATUS BIT(10)
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#define RTL8211F_INER_LINK_STATUS BIT(4)
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#define RTL821x_INSR 0x13
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#define RTL821x_PAGE_SELECT 0x1f
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#define RTL8211F_INSR 0x1d
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#define RTL8211F_TX_DELAY BIT(8)
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#define RTL8201F_ISR 0x1e
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#define RTL8201F_IER 0x13
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MODULE_DESCRIPTION("Realtek PHY driver");
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MODULE_AUTHOR("Johnson Leung");
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MODULE_LICENSE("GPL");
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static int rtl8211x_page_read(struct phy_device *phydev, u16 page, u16 address)
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{
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int ret;
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ret = phy_write(phydev, RTL821x_PAGE_SELECT, page);
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if (ret)
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return ret;
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ret = phy_read(phydev, address);
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/* restore to default page 0 */
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phy_write(phydev, RTL821x_PAGE_SELECT, 0x0);
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return ret;
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}
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static int rtl8211x_page_write(struct phy_device *phydev, u16 page,
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u16 address, u16 val)
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{
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int ret;
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ret = phy_write(phydev, RTL821x_PAGE_SELECT, page);
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if (ret)
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return ret;
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ret = phy_write(phydev, address, val);
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/* restore to default page 0 */
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phy_write(phydev, RTL821x_PAGE_SELECT, 0x0);
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return ret;
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}
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static int rtl8201_ack_interrupt(struct phy_device *phydev)
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{
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int err;
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err = phy_read(phydev, RTL8201F_ISR);
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return (err < 0) ? err : 0;
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}
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static int rtl821x_ack_interrupt(struct phy_device *phydev)
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{
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int err;
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err = phy_read(phydev, RTL821x_INSR);
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return (err < 0) ? err : 0;
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}
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static int rtl8211f_ack_interrupt(struct phy_device *phydev)
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{
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int err;
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err = rtl8211x_page_read(phydev, 0xa43, RTL8211F_INSR);
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return (err < 0) ? err : 0;
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}
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static int rtl8201_config_intr(struct phy_device *phydev)
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{
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u16 val;
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
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val = BIT(13) | BIT(12) | BIT(11);
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else
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val = 0;
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return rtl8211x_page_write(phydev, 0x7, RTL8201F_IER, val);
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}
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static int rtl8211b_config_intr(struct phy_device *phydev)
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{
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int err;
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
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err = phy_write(phydev, RTL821x_INER,
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RTL8211B_INER_INIT);
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else
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err = phy_write(phydev, RTL821x_INER, 0);
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return err;
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}
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static int rtl8211e_config_intr(struct phy_device *phydev)
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{
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int err;
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
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err = phy_write(phydev, RTL821x_INER,
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RTL8211E_INER_LINK_STATUS);
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else
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err = phy_write(phydev, RTL821x_INER, 0);
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return err;
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}
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static int rtl8211f_config_intr(struct phy_device *phydev)
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{
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u16 val;
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
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val = RTL8211F_INER_LINK_STATUS;
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else
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val = 0;
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return rtl8211x_page_write(phydev, 0xa42, RTL821x_INER, val);
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}
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static int rtl8211f_config_init(struct phy_device *phydev)
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{
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int ret;
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u16 val;
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ret = genphy_config_init(phydev);
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if (ret < 0)
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return ret;
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ret = rtl8211x_page_read(phydev, 0xd08, 0x11);
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if (ret < 0)
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return ret;
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val = ret & 0xffff;
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/* enable TX-delay for rgmii-id and rgmii-txid, otherwise disable it */
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
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phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
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val |= RTL8211F_TX_DELAY;
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else
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val &= ~RTL8211F_TX_DELAY;
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ret = rtl8211x_page_write(phydev, 0xd08, 0x11, val);
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if (ret)
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return ret;
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return 0;
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}
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static struct phy_driver realtek_drvs[] = {
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{
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.phy_id = 0x00008201,
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.name = "RTL8201CP Ethernet",
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.phy_id_mask = 0x0000ffff,
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.features = PHY_BASIC_FEATURES,
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.flags = PHY_HAS_INTERRUPT,
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}, {
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.phy_id = 0x001cc816,
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.name = "RTL8201F 10/100Mbps Ethernet",
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.phy_id_mask = 0x001fffff,
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.features = PHY_BASIC_FEATURES,
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.flags = PHY_HAS_INTERRUPT,
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.ack_interrupt = &rtl8201_ack_interrupt,
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.config_intr = &rtl8201_config_intr,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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}, {
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.phy_id = 0x001cc912,
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.name = "RTL8211B Gigabit Ethernet",
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.phy_id_mask = 0x001fffff,
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.features = PHY_GBIT_FEATURES,
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.flags = PHY_HAS_INTERRUPT,
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.ack_interrupt = &rtl821x_ack_interrupt,
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.config_intr = &rtl8211b_config_intr,
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}, {
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.phy_id = 0x001cc914,
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.name = "RTL8211DN Gigabit Ethernet",
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.phy_id_mask = 0x001fffff,
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.features = PHY_GBIT_FEATURES,
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.flags = PHY_HAS_INTERRUPT,
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.ack_interrupt = rtl821x_ack_interrupt,
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.config_intr = rtl8211e_config_intr,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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}, {
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.phy_id = 0x001cc915,
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.name = "RTL8211E Gigabit Ethernet",
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.phy_id_mask = 0x001fffff,
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.features = PHY_GBIT_FEATURES,
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.flags = PHY_HAS_INTERRUPT,
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.ack_interrupt = &rtl821x_ack_interrupt,
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.config_intr = &rtl8211e_config_intr,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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}, {
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.phy_id = 0x001cc916,
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.name = "RTL8211F Gigabit Ethernet",
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.phy_id_mask = 0x001fffff,
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.features = PHY_GBIT_FEATURES,
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.flags = PHY_HAS_INTERRUPT,
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.config_init = &rtl8211f_config_init,
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.ack_interrupt = &rtl8211f_ack_interrupt,
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.config_intr = &rtl8211f_config_intr,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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},
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};
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module_phy_driver(realtek_drvs);
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static struct mdio_device_id __maybe_unused realtek_tbl[] = {
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{ 0x001cc816, 0x001fffff },
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{ 0x001cc912, 0x001fffff },
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{ 0x001cc914, 0x001fffff },
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{ 0x001cc915, 0x001fffff },
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{ 0x001cc916, 0x001fffff },
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{ }
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};
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MODULE_DEVICE_TABLE(mdio, realtek_tbl);
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