a7a3324a60
An underrun (playback) event occurs when the serializer transfer data from the XRBUF buffer to the XRSR shift register, but the XRBUF hasn't been filled. Similarly, the overrun (capture) event occurs when data from the XRSR shift register is transferred to the XRBUF but it hasn't been read yet. These events are handled as XRUN events that cause the pcm to stop. The stream has to be explicitly restarted by the userspace which ensures that after stopping/starting McASP the data transfer is aligned with DMA. The other possibility was to internally stop and start McASP without DMA even knowing about it. Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
307 lines
8 KiB
C
307 lines
8 KiB
C
/*
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* ALSA SoC McASP Audio Layer for TI DAVINCI processor
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*
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* MCASP related definitions
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*
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* Author: Nirmal Pandey <n-pandey@ti.com>,
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* Suresh Rajashekara <suresh.r@ti.com>
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* Steve Chen <schen@.mvista.com>
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*
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* Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
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* Copyright: (C) 2009 Texas Instruments, India
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef DAVINCI_MCASP_H
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#define DAVINCI_MCASP_H
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/*
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* McASP register definitions
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*/
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#define DAVINCI_MCASP_PID_REG 0x00
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#define DAVINCI_MCASP_PWREMUMGT_REG 0x04
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#define DAVINCI_MCASP_PFUNC_REG 0x10
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#define DAVINCI_MCASP_PDIR_REG 0x14
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#define DAVINCI_MCASP_PDOUT_REG 0x18
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#define DAVINCI_MCASP_PDSET_REG 0x1c
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#define DAVINCI_MCASP_PDCLR_REG 0x20
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#define DAVINCI_MCASP_TLGC_REG 0x30
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#define DAVINCI_MCASP_TLMR_REG 0x34
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#define DAVINCI_MCASP_GBLCTL_REG 0x44
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#define DAVINCI_MCASP_AMUTE_REG 0x48
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#define DAVINCI_MCASP_LBCTL_REG 0x4c
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#define DAVINCI_MCASP_TXDITCTL_REG 0x50
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#define DAVINCI_MCASP_GBLCTLR_REG 0x60
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#define DAVINCI_MCASP_RXMASK_REG 0x64
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#define DAVINCI_MCASP_RXFMT_REG 0x68
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#define DAVINCI_MCASP_RXFMCTL_REG 0x6c
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#define DAVINCI_MCASP_ACLKRCTL_REG 0x70
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#define DAVINCI_MCASP_AHCLKRCTL_REG 0x74
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#define DAVINCI_MCASP_RXTDM_REG 0x78
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#define DAVINCI_MCASP_EVTCTLR_REG 0x7c
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#define DAVINCI_MCASP_RXSTAT_REG 0x80
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#define DAVINCI_MCASP_RXTDMSLOT_REG 0x84
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#define DAVINCI_MCASP_RXCLKCHK_REG 0x88
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#define DAVINCI_MCASP_REVTCTL_REG 0x8c
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#define DAVINCI_MCASP_GBLCTLX_REG 0xa0
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#define DAVINCI_MCASP_TXMASK_REG 0xa4
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#define DAVINCI_MCASP_TXFMT_REG 0xa8
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#define DAVINCI_MCASP_TXFMCTL_REG 0xac
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#define DAVINCI_MCASP_ACLKXCTL_REG 0xb0
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#define DAVINCI_MCASP_AHCLKXCTL_REG 0xb4
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#define DAVINCI_MCASP_TXTDM_REG 0xb8
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#define DAVINCI_MCASP_EVTCTLX_REG 0xbc
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#define DAVINCI_MCASP_TXSTAT_REG 0xc0
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#define DAVINCI_MCASP_TXTDMSLOT_REG 0xc4
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#define DAVINCI_MCASP_TXCLKCHK_REG 0xc8
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#define DAVINCI_MCASP_XEVTCTL_REG 0xcc
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/* Left(even TDM Slot) Channel Status Register File */
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#define DAVINCI_MCASP_DITCSRA_REG 0x100
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/* Right(odd TDM slot) Channel Status Register File */
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#define DAVINCI_MCASP_DITCSRB_REG 0x118
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/* Left(even TDM slot) User Data Register File */
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#define DAVINCI_MCASP_DITUDRA_REG 0x130
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/* Right(odd TDM Slot) User Data Register File */
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#define DAVINCI_MCASP_DITUDRB_REG 0x148
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/* Serializer n Control Register */
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#define DAVINCI_MCASP_XRSRCTL_BASE_REG 0x180
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#define DAVINCI_MCASP_XRSRCTL_REG(n) (DAVINCI_MCASP_XRSRCTL_BASE_REG + \
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(n << 2))
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/* Transmit Buffer for Serializer n */
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#define DAVINCI_MCASP_TXBUF_REG 0x200
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/* Receive Buffer for Serializer n */
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#define DAVINCI_MCASP_RXBUF_REG 0x280
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/* McASP FIFO Registers */
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#define DAVINCI_MCASP_V2_AFIFO_BASE (0x1010)
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#define DAVINCI_MCASP_V3_AFIFO_BASE (0x1000)
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/* FIFO register offsets from AFIFO base */
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#define MCASP_WFIFOCTL_OFFSET (0x0)
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#define MCASP_WFIFOSTS_OFFSET (0x4)
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#define MCASP_RFIFOCTL_OFFSET (0x8)
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#define MCASP_RFIFOSTS_OFFSET (0xc)
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/*
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* DAVINCI_MCASP_PWREMUMGT_REG - Power Down and Emulation Management
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* Register Bits
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*/
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#define MCASP_FREE BIT(0)
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#define MCASP_SOFT BIT(1)
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/*
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* DAVINCI_MCASP_PFUNC_REG - Pin Function / GPIO Enable Register Bits
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*/
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#define AXR(n) (1<<n)
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#define PFUNC_AMUTE BIT(25)
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#define ACLKX BIT(26)
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#define AHCLKX BIT(27)
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#define AFSX BIT(28)
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#define ACLKR BIT(29)
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#define AHCLKR BIT(30)
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#define AFSR BIT(31)
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/*
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* DAVINCI_MCASP_PDIR_REG - Pin Direction Register Bits
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*/
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#define AXR(n) (1<<n)
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#define PDIR_AMUTE BIT(25)
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#define ACLKX BIT(26)
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#define AHCLKX BIT(27)
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#define AFSX BIT(28)
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#define ACLKR BIT(29)
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#define AHCLKR BIT(30)
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#define AFSR BIT(31)
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/*
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* DAVINCI_MCASP_TXDITCTL_REG - Transmit DIT Control Register Bits
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*/
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#define DITEN BIT(0) /* Transmit DIT mode enable/disable */
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#define VA BIT(2)
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#define VB BIT(3)
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/*
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* DAVINCI_MCASP_TXFMT_REG - Transmit Bitstream Format Register Bits
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*/
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#define TXROT(val) (val)
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#define TXSEL BIT(3)
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#define TXSSZ(val) (val<<4)
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#define TXPBIT(val) (val<<8)
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#define TXPAD(val) (val<<13)
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#define TXORD BIT(15)
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#define FSXDLY(val) (val<<16)
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/*
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* DAVINCI_MCASP_RXFMT_REG - Receive Bitstream Format Register Bits
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*/
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#define RXROT(val) (val)
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#define RXSEL BIT(3)
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#define RXSSZ(val) (val<<4)
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#define RXPBIT(val) (val<<8)
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#define RXPAD(val) (val<<13)
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#define RXORD BIT(15)
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#define FSRDLY(val) (val<<16)
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/*
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* DAVINCI_MCASP_TXFMCTL_REG - Transmit Frame Control Register Bits
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*/
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#define FSXPOL BIT(0)
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#define AFSXE BIT(1)
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#define FSXDUR BIT(4)
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#define FSXMOD(val) (val<<7)
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/*
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* DAVINCI_MCASP_RXFMCTL_REG - Receive Frame Control Register Bits
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*/
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#define FSRPOL BIT(0)
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#define AFSRE BIT(1)
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#define FSRDUR BIT(4)
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#define FSRMOD(val) (val<<7)
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/*
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* DAVINCI_MCASP_ACLKXCTL_REG - Transmit Clock Control Register Bits
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*/
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#define ACLKXDIV(val) (val)
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#define ACLKXE BIT(5)
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#define TX_ASYNC BIT(6)
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#define ACLKXPOL BIT(7)
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#define ACLKXDIV_MASK 0x1f
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/*
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* DAVINCI_MCASP_ACLKRCTL_REG Receive Clock Control Register Bits
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*/
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#define ACLKRDIV(val) (val)
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#define ACLKRE BIT(5)
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#define RX_ASYNC BIT(6)
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#define ACLKRPOL BIT(7)
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#define ACLKRDIV_MASK 0x1f
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/*
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* DAVINCI_MCASP_AHCLKXCTL_REG - High Frequency Transmit Clock Control
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* Register Bits
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*/
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#define AHCLKXDIV(val) (val)
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#define AHCLKXPOL BIT(14)
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#define AHCLKXE BIT(15)
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#define AHCLKXDIV_MASK 0xfff
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/*
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* DAVINCI_MCASP_AHCLKRCTL_REG - High Frequency Receive Clock Control
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* Register Bits
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*/
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#define AHCLKRDIV(val) (val)
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#define AHCLKRPOL BIT(14)
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#define AHCLKRE BIT(15)
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#define AHCLKRDIV_MASK 0xfff
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/*
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* DAVINCI_MCASP_XRSRCTL_BASE_REG - Serializer Control Register Bits
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*/
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#define MODE(val) (val)
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#define DISMOD (val)(val<<2)
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#define TXSTATE BIT(4)
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#define RXSTATE BIT(5)
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#define SRMOD_MASK 3
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#define SRMOD_INACTIVE 0
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/*
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* DAVINCI_MCASP_LBCTL_REG - Loop Back Control Register Bits
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*/
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#define LBEN BIT(0)
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#define LBORD BIT(1)
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#define LBGENMODE(val) (val<<2)
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/*
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* DAVINCI_MCASP_TXTDMSLOT_REG - Transmit TDM Slot Register configuration
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*/
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#define TXTDMS(n) (1<<n)
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/*
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* DAVINCI_MCASP_RXTDMSLOT_REG - Receive TDM Slot Register configuration
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*/
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#define RXTDMS(n) (1<<n)
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/*
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* DAVINCI_MCASP_GBLCTL_REG - Global Control Register Bits
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*/
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#define RXCLKRST BIT(0) /* Receiver Clock Divider Reset */
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#define RXHCLKRST BIT(1) /* Receiver High Frequency Clock Divider */
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#define RXSERCLR BIT(2) /* Receiver Serializer Clear */
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#define RXSMRST BIT(3) /* Receiver State Machine Reset */
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#define RXFSRST BIT(4) /* Frame Sync Generator Reset */
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#define TXCLKRST BIT(8) /* Transmitter Clock Divider Reset */
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#define TXHCLKRST BIT(9) /* Transmitter High Frequency Clock Divider*/
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#define TXSERCLR BIT(10) /* Transmit Serializer Clear */
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#define TXSMRST BIT(11) /* Transmitter State Machine Reset */
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#define TXFSRST BIT(12) /* Frame Sync Generator Reset */
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/*
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* DAVINCI_MCASP_TXSTAT_REG - Transmitter Status Register Bits
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* DAVINCI_MCASP_RXSTAT_REG - Receiver Status Register Bits
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*/
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#define XRERR BIT(8) /* Transmit/Receive error */
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#define XRDATA BIT(5) /* Transmit/Receive data ready */
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/*
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* DAVINCI_MCASP_AMUTE_REG - Mute Control Register Bits
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*/
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#define MUTENA(val) (val)
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#define MUTEINPOL BIT(2)
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#define MUTEINENA BIT(3)
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#define MUTEIN BIT(4)
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#define MUTER BIT(5)
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#define MUTEX BIT(6)
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#define MUTEFSR BIT(7)
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#define MUTEFSX BIT(8)
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#define MUTEBADCLKR BIT(9)
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#define MUTEBADCLKX BIT(10)
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#define MUTERXDMAERR BIT(11)
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#define MUTETXDMAERR BIT(12)
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/*
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* DAVINCI_MCASP_REVTCTL_REG - Receiver DMA Event Control Register bits
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*/
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#define RXDATADMADIS BIT(0)
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/*
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* DAVINCI_MCASP_XEVTCTL_REG - Transmitter DMA Event Control Register bits
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*/
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#define TXDATADMADIS BIT(0)
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/*
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* DAVINCI_MCASP_EVTCTLR_REG - Receiver Interrupt Control Register Bits
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*/
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#define ROVRN BIT(0)
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/*
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* DAVINCI_MCASP_EVTCTLX_REG - Transmitter Interrupt Control Register Bits
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*/
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#define XUNDRN BIT(0)
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/*
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* DAVINCI_MCASP_W[R]FIFOCTL - Write/Read FIFO Control Register bits
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*/
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#define FIFO_ENABLE BIT(16)
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#define NUMEVT_MASK (0xFF << 8)
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#define NUMEVT(x) (((x) & 0xFF) << 8)
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#define NUMDMA_MASK (0xFF)
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#endif /* DAVINCI_MCASP_H */
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