2763ea0585
Add DMA optional support to STM32 ADC, as there is a limited number DMA channels (request lines) that can be assigned to ADC. This way, driver may fall back using interrupts when all DMA channels are in use for other IPs. Use dma cyclic mode with two periods. Allow to tune period length by using watermark. Coherent memory is used for dma (max buffer size is fixed to PAGE_SIZE). Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
55 lines
1.9 KiB
C
55 lines
1.9 KiB
C
/*
|
|
* This file is part of STM32 ADC driver
|
|
*
|
|
* Copyright (C) 2016, STMicroelectronics - All Rights Reserved
|
|
* Author: Fabrice Gasnier <fabrice.gasnier@st.com>.
|
|
*
|
|
* License type: GPLv2
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify it
|
|
* under the terms of the GNU General Public License version 2 as published by
|
|
* the Free Software Foundation.
|
|
*
|
|
* This program is distributed in the hope that it will be useful, but
|
|
* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
|
* or FITNESS FOR A PARTICULAR PURPOSE.
|
|
* See the GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License along with
|
|
* this program. If not, see <http://www.gnu.org/licenses/>.
|
|
*/
|
|
|
|
#ifndef __STM32_ADC_H
|
|
#define __STM32_ADC_H
|
|
|
|
/*
|
|
* STM32 - ADC global register map
|
|
* ________________________________________________________
|
|
* | Offset | Register |
|
|
* --------------------------------------------------------
|
|
* | 0x000 | Master ADC1 |
|
|
* --------------------------------------------------------
|
|
* | 0x100 | Slave ADC2 |
|
|
* --------------------------------------------------------
|
|
* | 0x200 | Slave ADC3 |
|
|
* --------------------------------------------------------
|
|
* | 0x300 | Master & Slave common regs |
|
|
* --------------------------------------------------------
|
|
*/
|
|
#define STM32_ADC_MAX_ADCS 3
|
|
#define STM32_ADCX_COMN_OFFSET 0x300
|
|
|
|
/**
|
|
* struct stm32_adc_common - stm32 ADC driver common data (for all instances)
|
|
* @base: control registers base cpu addr
|
|
* @phys_base: control registers base physical addr
|
|
* @vref_mv: vref voltage (mv)
|
|
*/
|
|
struct stm32_adc_common {
|
|
void __iomem *base;
|
|
phys_addr_t phys_base;
|
|
int vref_mv;
|
|
};
|
|
|
|
#endif
|