![Mathieu Poirier](/assets/img/avatar_default.png)
The System Trace Macrocell (STM) is an IP block falling under the CoreSight umbrella. It's main purpose it so expose stimulus channels to any system component for the purpose of information logging. Bindings for this IP block adds a couple of items to the current mandatory definition for CoreSight components. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
233 lines
5.7 KiB
Plaintext
233 lines
5.7 KiB
Plaintext
* CoreSight Components:
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CoreSight components are compliant with the ARM CoreSight architecture
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specification and can be connected in various topologies to suit a particular
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SoCs tracing needs. These trace components can generally be classified as
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sinks, links and sources. Trace data produced by one or more sources flows
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through the intermediate links connecting the source to the currently selected
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sink. Each CoreSight component device should use these properties to describe
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its hardware characteristcs.
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* Required properties for all components *except* non-configurable replicators:
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* compatible: These have to be supplemented with "arm,primecell" as
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drivers are using the AMBA bus interface. Possible values include:
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- "arm,coresight-etb10", "arm,primecell";
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- "arm,coresight-tpiu", "arm,primecell";
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- "arm,coresight-tmc", "arm,primecell";
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- "arm,coresight-funnel", "arm,primecell";
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- "arm,coresight-etm3x", "arm,primecell";
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- "arm,coresight-etm4x", "arm,primecell";
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- "qcom,coresight-replicator1x", "arm,primecell";
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- "arm,coresight-stm", "arm,primecell"; [1]
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* reg: physical base address and length of the register
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set(s) of the component.
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* clocks: the clocks associated to this component.
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* clock-names: the name of the clocks referenced by the code.
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Since we are using the AMBA framework, the name of the clock
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providing the interconnect should be "apb_pclk", and some
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coresight blocks also have an additional clock "atclk", which
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clocks the core of that coresight component. The latter clock
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is optional.
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* port or ports: The representation of the component's port
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layout using the generic DT graph presentation found in
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"bindings/graph.txt".
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* Additional required properties for System Trace Macrocells (STM):
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* reg: along with the physical base address and length of the register
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set as described above, another entry is required to describe the
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mapping of the extended stimulus port area.
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* reg-names: the only acceptable values are "stm-base" and
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"stm-stimulus-base", each corresponding to the areas defined in "reg".
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* Required properties for devices that don't show up on the AMBA bus, such as
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non-configurable replicators:
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* compatible: Currently supported value is (note the absence of the
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AMBA markee):
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- "arm,coresight-replicator"
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* port or ports: same as above.
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* Optional properties for ETM/PTMs:
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* arm,cp14: must be present if the system accesses ETM/PTM management
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registers via co-processor 14.
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* cpu: the cpu phandle this ETM/PTM is affined to. When omitted the
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source is considered to belong to CPU0.
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* Optional property for TMC:
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* arm,buffer-size: size of contiguous buffer space for TMC ETR
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(embedded trace router)
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Example:
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1. Sinks
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etb@20010000 {
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compatible = "arm,coresight-etb10", "arm,primecell";
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reg = <0 0x20010000 0 0x1000>;
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clocks = <&oscclk6a>;
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clock-names = "apb_pclk";
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port {
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etb_in_port: endpoint@0 {
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slave-mode;
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remote-endpoint = <&replicator_out_port0>;
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};
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};
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};
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tpiu@20030000 {
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compatible = "arm,coresight-tpiu", "arm,primecell";
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reg = <0 0x20030000 0 0x1000>;
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clocks = <&oscclk6a>;
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clock-names = "apb_pclk";
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port {
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tpiu_in_port: endpoint@0 {
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slave-mode;
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remote-endpoint = <&replicator_out_port1>;
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};
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};
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};
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2. Links
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replicator {
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/* non-configurable replicators don't show up on the
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* AMBA bus. As such no need to add "arm,primecell".
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*/
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compatible = "arm,coresight-replicator";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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/* replicator output ports */
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port@0 {
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reg = <0>;
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replicator_out_port0: endpoint {
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remote-endpoint = <&etb_in_port>;
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};
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};
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port@1 {
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reg = <1>;
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replicator_out_port1: endpoint {
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remote-endpoint = <&tpiu_in_port>;
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};
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};
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/* replicator input port */
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port@2 {
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reg = <0>;
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replicator_in_port0: endpoint {
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slave-mode;
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remote-endpoint = <&funnel_out_port0>;
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};
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};
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};
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};
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funnel@20040000 {
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compatible = "arm,coresight-funnel", "arm,primecell";
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reg = <0 0x20040000 0 0x1000>;
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clocks = <&oscclk6a>;
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clock-names = "apb_pclk";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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/* funnel output port */
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port@0 {
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reg = <0>;
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funnel_out_port0: endpoint {
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remote-endpoint =
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<&replicator_in_port0>;
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};
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};
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/* funnel input ports */
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port@1 {
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reg = <0>;
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funnel_in_port0: endpoint {
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slave-mode;
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remote-endpoint = <&ptm0_out_port>;
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};
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};
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port@2 {
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reg = <1>;
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funnel_in_port1: endpoint {
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slave-mode;
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remote-endpoint = <&ptm1_out_port>;
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};
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};
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port@3 {
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reg = <2>;
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funnel_in_port2: endpoint {
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slave-mode;
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remote-endpoint = <&etm0_out_port>;
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};
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};
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};
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};
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3. Sources
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ptm@2201c000 {
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compatible = "arm,coresight-etm3x", "arm,primecell";
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reg = <0 0x2201c000 0 0x1000>;
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cpu = <&cpu0>;
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clocks = <&oscclk6a>;
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clock-names = "apb_pclk";
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port {
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ptm0_out_port: endpoint {
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remote-endpoint = <&funnel_in_port0>;
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};
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};
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};
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ptm@2201d000 {
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compatible = "arm,coresight-etm3x", "arm,primecell";
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reg = <0 0x2201d000 0 0x1000>;
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cpu = <&cpu1>;
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clocks = <&oscclk6a>;
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clock-names = "apb_pclk";
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port {
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ptm1_out_port: endpoint {
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remote-endpoint = <&funnel_in_port1>;
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};
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};
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};
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4. STM
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stm@20100000 {
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compatible = "arm,coresight-stm", "arm,primecell";
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reg = <0 0x20100000 0 0x1000>,
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<0 0x28000000 0 0x180000>;
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reg-names = "stm-base", "stm-stimulus-base";
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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port {
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stm_out_port: endpoint {
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remote-endpoint = <&main_funnel_in_port2>;
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};
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};
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};
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[1]. There is currently two version of STM: STM32 and STM500. Both
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have the same HW interface and as such don't need an explicit binding name.
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