7dca3343fc
This rework allows to address tow memory controllers. AT91SAM9263 and AT91SAM9G45 family have tow SDRAM or DDR/SDRAM controllers. Power management should take care of this. This patch modify the way RAM IP header files are implemented to allow access to registers of both controllers ; it also adds some macros. We also modify the power management files to use those modified header files. Slow clock (assembly) and regular power management functions are synchronized for setting of RAM self-refresh procedure: (lpr & ~AT91_DDRSDRC_LPCB) | AT91_DDRSDRC_LPCB_SELF_REFRESH Note that AT91RM9200 is not impacted by this modification. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Andrew Victor <linux@maxim.org.za> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
116 lines
4.2 KiB
C
116 lines
4.2 KiB
C
/*
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* arch/arm/mach-at91/include/mach/at91sam9260.h
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*
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* Copyright (C) 2007 Atmel Corporation
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*
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* Common definitions.
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* Based on AT91SAM9RL datasheet revision A. (Preliminary)
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive for
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* more details.
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*/
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#ifndef AT91SAM9RL_H
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#define AT91SAM9RL_H
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/*
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* Peripheral identifiers/interrupts.
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*/
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#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
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#define AT91_ID_SYS 1 /* System Controller */
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#define AT91SAM9RL_ID_PIOA 2 /* Parallel IO Controller A */
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#define AT91SAM9RL_ID_PIOB 3 /* Parallel IO Controller B */
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#define AT91SAM9RL_ID_PIOC 4 /* Parallel IO Controller C */
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#define AT91SAM9RL_ID_PIOD 5 /* Parallel IO Controller D */
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#define AT91SAM9RL_ID_US0 6 /* USART 0 */
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#define AT91SAM9RL_ID_US1 7 /* USART 1 */
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#define AT91SAM9RL_ID_US2 8 /* USART 2 */
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#define AT91SAM9RL_ID_US3 9 /* USART 3 */
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#define AT91SAM9RL_ID_MCI 10 /* Multimedia Card Interface */
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#define AT91SAM9RL_ID_TWI0 11 /* TWI 0 */
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#define AT91SAM9RL_ID_TWI1 12 /* TWI 1 */
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#define AT91SAM9RL_ID_SPI 13 /* Serial Peripheral Interface */
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#define AT91SAM9RL_ID_SSC0 14 /* Serial Synchronous Controller 0 */
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#define AT91SAM9RL_ID_SSC1 15 /* Serial Synchronous Controller 1 */
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#define AT91SAM9RL_ID_TC0 16 /* Timer Counter 0 */
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#define AT91SAM9RL_ID_TC1 17 /* Timer Counter 1 */
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#define AT91SAM9RL_ID_TC2 18 /* Timer Counter 2 */
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#define AT91SAM9RL_ID_PWMC 19 /* Pulse Width Modulation Controller */
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#define AT91SAM9RL_ID_TSC 20 /* Touch Screen Controller */
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#define AT91SAM9RL_ID_DMA 21 /* DMA Controller */
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#define AT91SAM9RL_ID_UDPHS 22 /* USB Device HS */
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#define AT91SAM9RL_ID_LCDC 23 /* LCD Controller */
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#define AT91SAM9RL_ID_AC97C 24 /* AC97 Controller */
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#define AT91SAM9RL_ID_IRQ0 31 /* Advanced Interrupt Controller (IRQ0) */
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/*
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* User Peripheral physical base addresses.
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*/
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#define AT91SAM9RL_BASE_TCB0 0xfffa0000
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#define AT91SAM9RL_BASE_TC0 0xfffa0000
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#define AT91SAM9RL_BASE_TC1 0xfffa0040
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#define AT91SAM9RL_BASE_TC2 0xfffa0080
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#define AT91SAM9RL_BASE_MCI 0xfffa4000
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#define AT91SAM9RL_BASE_TWI0 0xfffa8000
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#define AT91SAM9RL_BASE_TWI1 0xfffac000
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#define AT91SAM9RL_BASE_US0 0xfffb0000
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#define AT91SAM9RL_BASE_US1 0xfffb4000
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#define AT91SAM9RL_BASE_US2 0xfffb8000
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#define AT91SAM9RL_BASE_US3 0xfffbc000
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#define AT91SAM9RL_BASE_SSC0 0xfffc0000
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#define AT91SAM9RL_BASE_SSC1 0xfffc4000
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#define AT91SAM9RL_BASE_PWMC 0xfffc8000
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#define AT91SAM9RL_BASE_SPI 0xfffcc000
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#define AT91SAM9RL_BASE_TSC 0xfffd0000
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#define AT91SAM9RL_BASE_UDPHS 0xfffd4000
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#define AT91SAM9RL_BASE_AC97C 0xfffd8000
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#define AT91_BASE_SYS 0xffffc000
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/*
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* System Peripherals (offset from AT91_BASE_SYS)
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*/
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#define AT91_DMA (0xffffe600 - AT91_BASE_SYS)
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#define AT91_ECC (0xffffe800 - AT91_BASE_SYS)
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#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
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#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
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#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
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#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS)
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#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
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#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
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#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
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#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
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#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
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#define AT91_PIOD (0xfffffa00 - AT91_BASE_SYS)
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#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
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#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
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#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
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#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
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#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
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#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
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#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS)
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#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
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#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS)
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#define AT91_USART0 AT91SAM9RL_BASE_US0
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#define AT91_USART1 AT91SAM9RL_BASE_US1
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#define AT91_USART2 AT91SAM9RL_BASE_US2
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#define AT91_USART3 AT91SAM9RL_BASE_US3
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/*
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* Internal Memory.
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*/
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#define AT91SAM9RL_SRAM_BASE 0x00300000 /* Internal SRAM base address */
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#define AT91SAM9RL_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */
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#define AT91SAM9RL_ROM_BASE 0x00400000 /* Internal ROM base address */
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#define AT91SAM9RL_ROM_SIZE (2 * SZ_16K) /* Internal ROM size (32Kb) */
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#define AT91SAM9RL_LCDC_BASE 0x00500000 /* LCD Controller */
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#define AT91SAM9RL_UDPHS_FIFO 0x00600000 /* USB Device HS controller */
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#endif
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