![Linus Torvalds](/assets/img/avatar_default.png)
Unlike the board branch, this keeps having large sets of changes for every release, but that's quite expected and is so far working well. Most of this is plumbing for various device bindings and new platforms, but there's also a bit of cleanup and code removal for things that are moved from platform code to DT contents (some OMAP clock code in particular). There's also a pinctrl driver for tegra here (appropriately acked), that's introduced this way to make it more bisectable. I'm happy to say that there were no conflicts at all with this branch this release, which means that changes are flowing through our tree as expected instead of merged through driver maintainers (or at least not done with conflicts). There are several new boards added, and a couple of SoCs. In no particular order: * Rockchip RK3288 SoC support, including DTS for a dev board that they have seeded with some community developers. * Better support for Hardkernel Exynos4-based ODROID boards. * CCF conversions (and dtsi contents) for several Renesas platforms. * Gumstix Pepper (TI AM335x) board support * TI eval board support for AM437x * Allwinner A23 SoC, very similar to existing ones which mostly has resulted in DT changes for support. Also includes support for an Ippo tablet with the chipset. * Allwinner A31 Hummingbird board support, not to be confused with the SolidRun i.MX-based Hummingboard. * Tegra30 Apalis board support -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQIcBAABAgAGBQJT5DqvAAoJEIwa5zzehBx3tm0QAJk8zFyZuMhUPz6SoZTtO9ti zojZ2218oqLRDfLSYdJx/3QE7gb2ef0e2S6FrthecdAY8sqZzDddL7M/cCf1WSgy +D4dD1UEq+W/hOeEwIWyo3GR/71exgo/LMTIw8HOJh5c9fanQ2wNChNetCgh8b4u sVOEMmP1UTO2W7mH9cCRhWXFifBNi0yNl1QBYnLPzM2CbSEa4qQRarTn/94NSEiY U9XgzysklvYEW/30wcEkz8ZonKbJrtP+zEjODU4wN/muhHECeTehDrkJq0WEK/3C 3ptko2xQGURNaLM6HVvQS9qkXxyhCeZxqkELpjkjjM+YPFN8wdHu7gDctGZlDr39 LQ2pZF6K8vaFvxp3UM2wzdDeoNi3rxguzpFoBmfRP5NWguDrOvjT3w8W4hO9q04J 8SqMGca0av9myHmeSjtRRg5rmcC3kBbOgSN6siVJ8W80rHT7tnFjl6eCawDreQzn szFzGaOOUnf/kJ/00vzm1dCuluowFPdSYgW3aamZhfkqu2qYJ8Ztuooz5eZGKtex zlUfKtpL26gnamoUT42K7E8J968AjHjUc/zimwYzIgHCzTTApYGJQcbD/Y28b8QH gTvhRxP+0kFb+NNq4IHStVMvJrFOPvzOHXcL8x07HqTxrl7W4XoW+KJxCJOk433W 5NJ9s4tEmiTRMtFL1kv6 =xxlY -----END PGP SIGNATURE----- Merge tag 'dt-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC device-tree changes from Olof Johansson: "Unlike the board branch, this keeps having large sets of changes for every release, but that's quite expected and is so far working well. Most of this is plumbing for various device bindings and new platforms, but there's also a bit of cleanup and code removal for things that are moved from platform code to DT contents (some OMAP clock code in particular). There's also a pinctrl driver for tegra here (appropriately acked), that's introduced this way to make it more bisectable. I'm happy to say that there were no conflicts at all with this branch this release, which means that changes are flowing through our tree as expected instead of merged through driver maintainers (or at least not done with conflicts). There are several new boards added, and a couple of SoCs. In no particular order: - Rockchip RK3288 SoC support, including DTS for a dev board that they have seeded with some community developers. - Better support for Hardkernel Exynos4-based ODROID boards. - CCF conversions (and dtsi contents) for several Renesas platforms. - Gumstix Pepper (TI AM335x) board support - TI eval board support for AM437x - Allwinner A23 SoC, very similar to existing ones which mostly has resulted in DT changes for support. Also includes support for an Ippo tablet with the chipset. - Allwinner A31 Hummingbird board support, not to be confused with the SolidRun i.MX-based Hummingboard. - Tegra30 Apalis board support" * tag 'dt-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (334 commits) ARM: dts: Enable USB host0 (EHCI) on rk3288-evb ARM: dts: add rk3288 ehci usb devices ARM: dts: Turn on USB host vbus on rk3288-evb ARM: tegra: apalis t30: fix device tree compatible node ARM: tegra: paz00: Fix some indentation inconsistencies ARM: zynq: DT: Clarify Xilinx Zynq platform ARM: dts: rockchip: add watchdog node ARM: dts: rockchip: remove pinctrl setting from radxarock uart2 ARM: dts: Add missing pinctrl for uart0/1 for exynos3250 ARM: dts: Remove duplicate 'interrput-parent' property for exynos3250 ARM: dts: Add TMU dt node to monitor the temperature for exynos3250 ARM: dts: Specify MAX77686 pmic interrupt for exynos5250-smdk5250 ARM: dts: cypress,cyapa trackpad is exynos5250-Snow only ARM: dts: max77686 is exynos5250-snow only ARM: zynq: DT: Remove DMA from board DTs ARM: zynq: DT: Add CAN node ARM: EXYNOS: Add exynos5260 PMU compatible string to DT match table ARM: dts: Add PMU DT node for exynos5260 SoC ARM: EXYNOS: Add support for Exynos5410 PMU ARM: dts: Add PMU to exynos5410 ...
805 lines
20 KiB
C
805 lines
20 KiB
C
/*
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* sh73a0 processor support
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*
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* Copyright (C) 2010 Takashi Yoshii
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* Copyright (C) 2010 Magnus Damm
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* Copyright (C) 2008 Yoshihiro Shimoda
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/platform_device.h>
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#include <linux/of_platform.h>
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#include <linux/delay.h>
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#include <linux/input.h>
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#include <linux/io.h>
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#include <linux/serial_sci.h>
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#include <linux/sh_dma.h>
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#include <linux/sh_timer.h>
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#include <linux/platform_data/sh_ipmmu.h>
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#include <linux/platform_data/irq-renesas-intc-irqpin.h>
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#include <asm/mach-types.h>
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#include <asm/mach/map.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/time.h>
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#include "common.h"
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#include "dma-register.h"
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#include "irqs.h"
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#include "sh73a0.h"
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static struct map_desc sh73a0_io_desc[] __initdata = {
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/* create a 1:1 entity map for 0xe6xxxxxx
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* used by CPGA, INTC and PFC.
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*/
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{
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.virtual = 0xe6000000,
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.pfn = __phys_to_pfn(0xe6000000),
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.length = 256 << 20,
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.type = MT_DEVICE_NONSHARED
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},
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};
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void __init sh73a0_map_io(void)
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{
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iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc));
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}
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/* PFC */
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static struct resource pfc_resources[] __initdata = {
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DEFINE_RES_MEM(0xe6050000, 0x8000),
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DEFINE_RES_MEM(0xe605801c, 0x000c),
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};
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void __init sh73a0_pinmux_init(void)
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{
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platform_device_register_simple("pfc-sh73a0", -1, pfc_resources,
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ARRAY_SIZE(pfc_resources));
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}
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/* SCIF */
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#define SH73A0_SCIF(scif_type, index, baseaddr, irq) \
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static struct plat_sci_port scif##index##_platform_data = { \
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.type = scif_type, \
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.flags = UPF_BOOT_AUTOCONF, \
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.scscr = SCSCR_RE | SCSCR_TE, \
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}; \
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\
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static struct resource scif##index##_resources[] = { \
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DEFINE_RES_MEM(baseaddr, 0x100), \
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DEFINE_RES_IRQ(irq), \
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}; \
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\
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static struct platform_device scif##index##_device = { \
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.name = "sh-sci", \
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.id = index, \
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.resource = scif##index##_resources, \
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.num_resources = ARRAY_SIZE(scif##index##_resources), \
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.dev = { \
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.platform_data = &scif##index##_platform_data, \
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}, \
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}
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SH73A0_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(72));
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SH73A0_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(73));
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SH73A0_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(74));
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SH73A0_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(75));
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SH73A0_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(78));
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SH73A0_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(79));
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SH73A0_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(156));
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SH73A0_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(143));
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SH73A0_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(80));
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static struct sh_timer_config cmt1_platform_data = {
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.channels_mask = 0x3f,
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};
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static struct resource cmt1_resources[] = {
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DEFINE_RES_MEM(0xe6138000, 0x200),
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DEFINE_RES_IRQ(gic_spi(65)),
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};
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static struct platform_device cmt1_device = {
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.name = "sh-cmt-48",
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.id = 1,
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.dev = {
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.platform_data = &cmt1_platform_data,
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},
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.resource = cmt1_resources,
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.num_resources = ARRAY_SIZE(cmt1_resources),
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};
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/* TMU */
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static struct sh_timer_config tmu0_platform_data = {
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.channels_mask = 7,
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};
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static struct resource tmu0_resources[] = {
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DEFINE_RES_MEM(0xfff60000, 0x2c),
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DEFINE_RES_IRQ(intcs_evt2irq(0xe80)),
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DEFINE_RES_IRQ(intcs_evt2irq(0xea0)),
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DEFINE_RES_IRQ(intcs_evt2irq(0xec0)),
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};
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static struct platform_device tmu0_device = {
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.name = "sh-tmu",
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.id = 0,
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.dev = {
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.platform_data = &tmu0_platform_data,
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},
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.resource = tmu0_resources,
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.num_resources = ARRAY_SIZE(tmu0_resources),
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};
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static struct resource i2c0_resources[] = {
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[0] = DEFINE_RES_MEM(0xe6820000, 0x426),
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[1] = {
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.start = gic_spi(167),
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.end = gic_spi(170),
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct resource i2c1_resources[] = {
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[0] = DEFINE_RES_MEM(0xe6822000, 0x426),
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[1] = {
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.start = gic_spi(51),
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.end = gic_spi(54),
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct resource i2c2_resources[] = {
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[0] = DEFINE_RES_MEM(0xe6824000, 0x426),
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[1] = {
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.start = gic_spi(171),
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.end = gic_spi(174),
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct resource i2c3_resources[] = {
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[0] = DEFINE_RES_MEM(0xe6826000, 0x426),
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[1] = {
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.start = gic_spi(183),
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.end = gic_spi(186),
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct resource i2c4_resources[] = {
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[0] = DEFINE_RES_MEM(0xe6828000, 0x426),
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[1] = {
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.start = gic_spi(187),
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.end = gic_spi(190),
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device i2c0_device = {
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.name = "i2c-sh_mobile",
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.id = 0,
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.resource = i2c0_resources,
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.num_resources = ARRAY_SIZE(i2c0_resources),
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};
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static struct platform_device i2c1_device = {
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.name = "i2c-sh_mobile",
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.id = 1,
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.resource = i2c1_resources,
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.num_resources = ARRAY_SIZE(i2c1_resources),
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};
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static struct platform_device i2c2_device = {
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.name = "i2c-sh_mobile",
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.id = 2,
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.resource = i2c2_resources,
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.num_resources = ARRAY_SIZE(i2c2_resources),
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};
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static struct platform_device i2c3_device = {
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.name = "i2c-sh_mobile",
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.id = 3,
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.resource = i2c3_resources,
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.num_resources = ARRAY_SIZE(i2c3_resources),
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};
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static struct platform_device i2c4_device = {
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.name = "i2c-sh_mobile",
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.id = 4,
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.resource = i2c4_resources,
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.num_resources = ARRAY_SIZE(i2c4_resources),
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};
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static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = {
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{
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.slave_id = SHDMA_SLAVE_SCIF0_TX,
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.addr = 0xe6c40020,
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.chcr = CHCR_TX(XMIT_SZ_8BIT),
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.mid_rid = 0x21,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF0_RX,
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.addr = 0xe6c40024,
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.chcr = CHCR_RX(XMIT_SZ_8BIT),
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.mid_rid = 0x22,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF1_TX,
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.addr = 0xe6c50020,
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.chcr = CHCR_TX(XMIT_SZ_8BIT),
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.mid_rid = 0x25,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF1_RX,
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.addr = 0xe6c50024,
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.chcr = CHCR_RX(XMIT_SZ_8BIT),
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.mid_rid = 0x26,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF2_TX,
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.addr = 0xe6c60020,
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.chcr = CHCR_TX(XMIT_SZ_8BIT),
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.mid_rid = 0x29,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF2_RX,
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.addr = 0xe6c60024,
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.chcr = CHCR_RX(XMIT_SZ_8BIT),
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.mid_rid = 0x2a,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF3_TX,
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.addr = 0xe6c70020,
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.chcr = CHCR_TX(XMIT_SZ_8BIT),
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.mid_rid = 0x2d,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF3_RX,
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.addr = 0xe6c70024,
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.chcr = CHCR_RX(XMIT_SZ_8BIT),
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.mid_rid = 0x2e,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF4_TX,
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.addr = 0xe6c80020,
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.chcr = CHCR_TX(XMIT_SZ_8BIT),
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.mid_rid = 0x39,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF4_RX,
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.addr = 0xe6c80024,
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.chcr = CHCR_RX(XMIT_SZ_8BIT),
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.mid_rid = 0x3a,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF5_TX,
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.addr = 0xe6cb0020,
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.chcr = CHCR_TX(XMIT_SZ_8BIT),
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.mid_rid = 0x35,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF5_RX,
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.addr = 0xe6cb0024,
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.chcr = CHCR_RX(XMIT_SZ_8BIT),
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.mid_rid = 0x36,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF6_TX,
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.addr = 0xe6cc0020,
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.chcr = CHCR_TX(XMIT_SZ_8BIT),
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.mid_rid = 0x1d,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF6_RX,
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.addr = 0xe6cc0024,
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.chcr = CHCR_RX(XMIT_SZ_8BIT),
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.mid_rid = 0x1e,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF7_TX,
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.addr = 0xe6cd0020,
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.chcr = CHCR_TX(XMIT_SZ_8BIT),
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.mid_rid = 0x19,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF7_RX,
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.addr = 0xe6cd0024,
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.chcr = CHCR_RX(XMIT_SZ_8BIT),
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.mid_rid = 0x1a,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF8_TX,
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.addr = 0xe6c30040,
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.chcr = CHCR_TX(XMIT_SZ_8BIT),
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.mid_rid = 0x3d,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF8_RX,
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.addr = 0xe6c30060,
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.chcr = CHCR_RX(XMIT_SZ_8BIT),
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.mid_rid = 0x3e,
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}, {
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.slave_id = SHDMA_SLAVE_SDHI0_TX,
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.addr = 0xee100030,
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.chcr = CHCR_TX(XMIT_SZ_16BIT),
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.mid_rid = 0xc1,
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}, {
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.slave_id = SHDMA_SLAVE_SDHI0_RX,
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.addr = 0xee100030,
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.chcr = CHCR_RX(XMIT_SZ_16BIT),
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.mid_rid = 0xc2,
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}, {
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.slave_id = SHDMA_SLAVE_SDHI1_TX,
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.addr = 0xee120030,
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.chcr = CHCR_TX(XMIT_SZ_16BIT),
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.mid_rid = 0xc9,
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}, {
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.slave_id = SHDMA_SLAVE_SDHI1_RX,
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.addr = 0xee120030,
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.chcr = CHCR_RX(XMIT_SZ_16BIT),
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.mid_rid = 0xca,
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}, {
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.slave_id = SHDMA_SLAVE_SDHI2_TX,
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.addr = 0xee140030,
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.chcr = CHCR_TX(XMIT_SZ_16BIT),
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.mid_rid = 0xcd,
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}, {
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.slave_id = SHDMA_SLAVE_SDHI2_RX,
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.addr = 0xee140030,
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.chcr = CHCR_RX(XMIT_SZ_16BIT),
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.mid_rid = 0xce,
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}, {
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.slave_id = SHDMA_SLAVE_MMCIF_TX,
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.addr = 0xe6bd0034,
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.chcr = CHCR_TX(XMIT_SZ_32BIT),
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.mid_rid = 0xd1,
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}, {
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.slave_id = SHDMA_SLAVE_MMCIF_RX,
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.addr = 0xe6bd0034,
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.chcr = CHCR_RX(XMIT_SZ_32BIT),
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.mid_rid = 0xd2,
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},
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};
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#define DMAE_CHANNEL(_offset) \
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{ \
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.offset = _offset - 0x20, \
|
|
.dmars = _offset - 0x20 + 0x40, \
|
|
}
|
|
|
|
static const struct sh_dmae_channel sh73a0_dmae_channels[] = {
|
|
DMAE_CHANNEL(0x8000),
|
|
DMAE_CHANNEL(0x8080),
|
|
DMAE_CHANNEL(0x8100),
|
|
DMAE_CHANNEL(0x8180),
|
|
DMAE_CHANNEL(0x8200),
|
|
DMAE_CHANNEL(0x8280),
|
|
DMAE_CHANNEL(0x8300),
|
|
DMAE_CHANNEL(0x8380),
|
|
DMAE_CHANNEL(0x8400),
|
|
DMAE_CHANNEL(0x8480),
|
|
DMAE_CHANNEL(0x8500),
|
|
DMAE_CHANNEL(0x8580),
|
|
DMAE_CHANNEL(0x8600),
|
|
DMAE_CHANNEL(0x8680),
|
|
DMAE_CHANNEL(0x8700),
|
|
DMAE_CHANNEL(0x8780),
|
|
DMAE_CHANNEL(0x8800),
|
|
DMAE_CHANNEL(0x8880),
|
|
DMAE_CHANNEL(0x8900),
|
|
DMAE_CHANNEL(0x8980),
|
|
};
|
|
|
|
static struct sh_dmae_pdata sh73a0_dmae_platform_data = {
|
|
.slave = sh73a0_dmae_slaves,
|
|
.slave_num = ARRAY_SIZE(sh73a0_dmae_slaves),
|
|
.channel = sh73a0_dmae_channels,
|
|
.channel_num = ARRAY_SIZE(sh73a0_dmae_channels),
|
|
.ts_low_shift = TS_LOW_SHIFT,
|
|
.ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
|
|
.ts_high_shift = TS_HI_SHIFT,
|
|
.ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
|
|
.ts_shift = dma_ts_shift,
|
|
.ts_shift_num = ARRAY_SIZE(dma_ts_shift),
|
|
.dmaor_init = DMAOR_DME,
|
|
};
|
|
|
|
static struct resource sh73a0_dmae_resources[] = {
|
|
DEFINE_RES_MEM(0xfe000020, 0x89e0),
|
|
{
|
|
.name = "error_irq",
|
|
.start = gic_spi(129),
|
|
.end = gic_spi(129),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
{
|
|
/* IRQ for channels 0-19 */
|
|
.start = gic_spi(109),
|
|
.end = gic_spi(128),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device dma0_device = {
|
|
.name = "sh-dma-engine",
|
|
.id = 0,
|
|
.resource = sh73a0_dmae_resources,
|
|
.num_resources = ARRAY_SIZE(sh73a0_dmae_resources),
|
|
.dev = {
|
|
.platform_data = &sh73a0_dmae_platform_data,
|
|
},
|
|
};
|
|
|
|
/* MPDMAC */
|
|
static const struct sh_dmae_slave_config sh73a0_mpdma_slaves[] = {
|
|
{
|
|
.slave_id = SHDMA_SLAVE_FSI2A_RX,
|
|
.addr = 0xec230020,
|
|
.chcr = CHCR_RX(XMIT_SZ_32BIT),
|
|
.mid_rid = 0xd6, /* CHECK ME */
|
|
}, {
|
|
.slave_id = SHDMA_SLAVE_FSI2A_TX,
|
|
.addr = 0xec230024,
|
|
.chcr = CHCR_TX(XMIT_SZ_32BIT),
|
|
.mid_rid = 0xd5, /* CHECK ME */
|
|
}, {
|
|
.slave_id = SHDMA_SLAVE_FSI2C_RX,
|
|
.addr = 0xec230060,
|
|
.chcr = CHCR_RX(XMIT_SZ_32BIT),
|
|
.mid_rid = 0xda, /* CHECK ME */
|
|
}, {
|
|
.slave_id = SHDMA_SLAVE_FSI2C_TX,
|
|
.addr = 0xec230064,
|
|
.chcr = CHCR_TX(XMIT_SZ_32BIT),
|
|
.mid_rid = 0xd9, /* CHECK ME */
|
|
}, {
|
|
.slave_id = SHDMA_SLAVE_FSI2B_RX,
|
|
.addr = 0xec240020,
|
|
.chcr = CHCR_RX(XMIT_SZ_32BIT),
|
|
.mid_rid = 0x8e, /* CHECK ME */
|
|
}, {
|
|
.slave_id = SHDMA_SLAVE_FSI2B_TX,
|
|
.addr = 0xec240024,
|
|
.chcr = CHCR_RX(XMIT_SZ_32BIT),
|
|
.mid_rid = 0x8d, /* CHECK ME */
|
|
}, {
|
|
.slave_id = SHDMA_SLAVE_FSI2D_RX,
|
|
.addr = 0xec240060,
|
|
.chcr = CHCR_RX(XMIT_SZ_32BIT),
|
|
.mid_rid = 0x9a, /* CHECK ME */
|
|
},
|
|
};
|
|
|
|
#define MPDMA_CHANNEL(a, b, c) \
|
|
{ \
|
|
.offset = a, \
|
|
.dmars = b, \
|
|
.dmars_bit = c, \
|
|
.chclr_offset = (0x220 - 0x20) + a \
|
|
}
|
|
|
|
static const struct sh_dmae_channel sh73a0_mpdma_channels[] = {
|
|
MPDMA_CHANNEL(0x00, 0, 0),
|
|
MPDMA_CHANNEL(0x10, 0, 8),
|
|
MPDMA_CHANNEL(0x20, 4, 0),
|
|
MPDMA_CHANNEL(0x30, 4, 8),
|
|
MPDMA_CHANNEL(0x50, 8, 0),
|
|
MPDMA_CHANNEL(0x70, 8, 8),
|
|
};
|
|
|
|
static struct sh_dmae_pdata sh73a0_mpdma_platform_data = {
|
|
.slave = sh73a0_mpdma_slaves,
|
|
.slave_num = ARRAY_SIZE(sh73a0_mpdma_slaves),
|
|
.channel = sh73a0_mpdma_channels,
|
|
.channel_num = ARRAY_SIZE(sh73a0_mpdma_channels),
|
|
.ts_low_shift = TS_LOW_SHIFT,
|
|
.ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
|
|
.ts_high_shift = TS_HI_SHIFT,
|
|
.ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
|
|
.ts_shift = dma_ts_shift,
|
|
.ts_shift_num = ARRAY_SIZE(dma_ts_shift),
|
|
.dmaor_init = DMAOR_DME,
|
|
.chclr_present = 1,
|
|
};
|
|
|
|
/* Resource order important! */
|
|
static struct resource sh73a0_mpdma_resources[] = {
|
|
/* Channel registers and DMAOR */
|
|
DEFINE_RES_MEM(0xec618020, 0x270),
|
|
/* DMARSx */
|
|
DEFINE_RES_MEM(0xec619000, 0xc),
|
|
{
|
|
.name = "error_irq",
|
|
.start = gic_spi(181),
|
|
.end = gic_spi(181),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
{
|
|
/* IRQ for channels 0-5 */
|
|
.start = gic_spi(175),
|
|
.end = gic_spi(180),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device mpdma0_device = {
|
|
.name = "sh-dma-engine",
|
|
.id = 1,
|
|
.resource = sh73a0_mpdma_resources,
|
|
.num_resources = ARRAY_SIZE(sh73a0_mpdma_resources),
|
|
.dev = {
|
|
.platform_data = &sh73a0_mpdma_platform_data,
|
|
},
|
|
};
|
|
|
|
static struct resource pmu_resources[] = {
|
|
[0] = {
|
|
.start = gic_spi(55),
|
|
.end = gic_spi(55),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
[1] = {
|
|
.start = gic_spi(56),
|
|
.end = gic_spi(56),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device pmu_device = {
|
|
.name = "arm-pmu",
|
|
.id = -1,
|
|
.num_resources = ARRAY_SIZE(pmu_resources),
|
|
.resource = pmu_resources,
|
|
};
|
|
|
|
/* an IPMMU module for ICB */
|
|
static struct resource ipmmu_resources[] = {
|
|
DEFINE_RES_MEM(0xfe951000, 0x100),
|
|
};
|
|
|
|
static const char * const ipmmu_dev_names[] = {
|
|
"sh_mobile_lcdc_fb.0",
|
|
};
|
|
|
|
static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
|
|
.dev_names = ipmmu_dev_names,
|
|
.num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
|
|
};
|
|
|
|
static struct platform_device ipmmu_device = {
|
|
.name = "ipmmu",
|
|
.id = -1,
|
|
.dev = {
|
|
.platform_data = &ipmmu_platform_data,
|
|
},
|
|
.resource = ipmmu_resources,
|
|
.num_resources = ARRAY_SIZE(ipmmu_resources),
|
|
};
|
|
|
|
static struct renesas_intc_irqpin_config irqpin0_platform_data = {
|
|
.irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
|
|
};
|
|
|
|
static struct resource irqpin0_resources[] = {
|
|
DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */
|
|
DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */
|
|
DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */
|
|
DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */
|
|
DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */
|
|
DEFINE_RES_IRQ(gic_spi(1)), /* IRQ0 */
|
|
DEFINE_RES_IRQ(gic_spi(2)), /* IRQ1 */
|
|
DEFINE_RES_IRQ(gic_spi(3)), /* IRQ2 */
|
|
DEFINE_RES_IRQ(gic_spi(4)), /* IRQ3 */
|
|
DEFINE_RES_IRQ(gic_spi(5)), /* IRQ4 */
|
|
DEFINE_RES_IRQ(gic_spi(6)), /* IRQ5 */
|
|
DEFINE_RES_IRQ(gic_spi(7)), /* IRQ6 */
|
|
DEFINE_RES_IRQ(gic_spi(8)), /* IRQ7 */
|
|
};
|
|
|
|
static struct platform_device irqpin0_device = {
|
|
.name = "renesas_intc_irqpin",
|
|
.id = 0,
|
|
.resource = irqpin0_resources,
|
|
.num_resources = ARRAY_SIZE(irqpin0_resources),
|
|
.dev = {
|
|
.platform_data = &irqpin0_platform_data,
|
|
},
|
|
};
|
|
|
|
static struct renesas_intc_irqpin_config irqpin1_platform_data = {
|
|
.irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */
|
|
.control_parent = true, /* Disable spurious IRQ10 */
|
|
};
|
|
|
|
static struct resource irqpin1_resources[] = {
|
|
DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */
|
|
DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */
|
|
DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */
|
|
DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */
|
|
DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */
|
|
DEFINE_RES_IRQ(gic_spi(9)), /* IRQ8 */
|
|
DEFINE_RES_IRQ(gic_spi(10)), /* IRQ9 */
|
|
DEFINE_RES_IRQ(gic_spi(11)), /* IRQ10 */
|
|
DEFINE_RES_IRQ(gic_spi(12)), /* IRQ11 */
|
|
DEFINE_RES_IRQ(gic_spi(13)), /* IRQ12 */
|
|
DEFINE_RES_IRQ(gic_spi(14)), /* IRQ13 */
|
|
DEFINE_RES_IRQ(gic_spi(15)), /* IRQ14 */
|
|
DEFINE_RES_IRQ(gic_spi(16)), /* IRQ15 */
|
|
};
|
|
|
|
static struct platform_device irqpin1_device = {
|
|
.name = "renesas_intc_irqpin",
|
|
.id = 1,
|
|
.resource = irqpin1_resources,
|
|
.num_resources = ARRAY_SIZE(irqpin1_resources),
|
|
.dev = {
|
|
.platform_data = &irqpin1_platform_data,
|
|
},
|
|
};
|
|
|
|
static struct renesas_intc_irqpin_config irqpin2_platform_data = {
|
|
.irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
|
|
};
|
|
|
|
static struct resource irqpin2_resources[] = {
|
|
DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */
|
|
DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI20A */
|
|
DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ20A */
|
|
DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK20A */
|
|
DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR20A */
|
|
DEFINE_RES_IRQ(gic_spi(17)), /* IRQ16 */
|
|
DEFINE_RES_IRQ(gic_spi(18)), /* IRQ17 */
|
|
DEFINE_RES_IRQ(gic_spi(19)), /* IRQ18 */
|
|
DEFINE_RES_IRQ(gic_spi(20)), /* IRQ19 */
|
|
DEFINE_RES_IRQ(gic_spi(21)), /* IRQ20 */
|
|
DEFINE_RES_IRQ(gic_spi(22)), /* IRQ21 */
|
|
DEFINE_RES_IRQ(gic_spi(23)), /* IRQ22 */
|
|
DEFINE_RES_IRQ(gic_spi(24)), /* IRQ23 */
|
|
};
|
|
|
|
static struct platform_device irqpin2_device = {
|
|
.name = "renesas_intc_irqpin",
|
|
.id = 2,
|
|
.resource = irqpin2_resources,
|
|
.num_resources = ARRAY_SIZE(irqpin2_resources),
|
|
.dev = {
|
|
.platform_data = &irqpin2_platform_data,
|
|
},
|
|
};
|
|
|
|
static struct renesas_intc_irqpin_config irqpin3_platform_data = {
|
|
.irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
|
|
};
|
|
|
|
static struct resource irqpin3_resources[] = {
|
|
DEFINE_RES_MEM(0xe690000c, 4), /* ICR4A */
|
|
DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */
|
|
DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */
|
|
DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */
|
|
DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */
|
|
DEFINE_RES_IRQ(gic_spi(25)), /* IRQ24 */
|
|
DEFINE_RES_IRQ(gic_spi(26)), /* IRQ25 */
|
|
DEFINE_RES_IRQ(gic_spi(27)), /* IRQ26 */
|
|
DEFINE_RES_IRQ(gic_spi(28)), /* IRQ27 */
|
|
DEFINE_RES_IRQ(gic_spi(29)), /* IRQ28 */
|
|
DEFINE_RES_IRQ(gic_spi(30)), /* IRQ29 */
|
|
DEFINE_RES_IRQ(gic_spi(31)), /* IRQ30 */
|
|
DEFINE_RES_IRQ(gic_spi(32)), /* IRQ31 */
|
|
};
|
|
|
|
static struct platform_device irqpin3_device = {
|
|
.name = "renesas_intc_irqpin",
|
|
.id = 3,
|
|
.resource = irqpin3_resources,
|
|
.num_resources = ARRAY_SIZE(irqpin3_resources),
|
|
.dev = {
|
|
.platform_data = &irqpin3_platform_data,
|
|
},
|
|
};
|
|
|
|
static struct platform_device *sh73a0_devices_dt[] __initdata = {
|
|
&cmt1_device,
|
|
};
|
|
|
|
static struct platform_device *sh73a0_early_devices[] __initdata = {
|
|
&scif0_device,
|
|
&scif1_device,
|
|
&scif2_device,
|
|
&scif3_device,
|
|
&scif4_device,
|
|
&scif5_device,
|
|
&scif6_device,
|
|
&scif7_device,
|
|
&scif8_device,
|
|
&tmu0_device,
|
|
&ipmmu_device,
|
|
};
|
|
|
|
static struct platform_device *sh73a0_late_devices[] __initdata = {
|
|
&i2c0_device,
|
|
&i2c1_device,
|
|
&i2c2_device,
|
|
&i2c3_device,
|
|
&i2c4_device,
|
|
&dma0_device,
|
|
&mpdma0_device,
|
|
&pmu_device,
|
|
&irqpin0_device,
|
|
&irqpin1_device,
|
|
&irqpin2_device,
|
|
&irqpin3_device,
|
|
};
|
|
|
|
#define SRCR2 IOMEM(0xe61580b0)
|
|
|
|
void __init sh73a0_add_standard_devices(void)
|
|
{
|
|
/* Clear software reset bit on SY-DMAC module */
|
|
__raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2);
|
|
|
|
platform_add_devices(sh73a0_devices_dt,
|
|
ARRAY_SIZE(sh73a0_devices_dt));
|
|
platform_add_devices(sh73a0_early_devices,
|
|
ARRAY_SIZE(sh73a0_early_devices));
|
|
platform_add_devices(sh73a0_late_devices,
|
|
ARRAY_SIZE(sh73a0_late_devices));
|
|
}
|
|
|
|
void __init sh73a0_init_delay(void)
|
|
{
|
|
shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */
|
|
}
|
|
|
|
/* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
|
|
void __init __weak sh73a0_register_twd(void) { }
|
|
|
|
void __init sh73a0_earlytimer_init(void)
|
|
{
|
|
sh73a0_init_delay();
|
|
sh73a0_clock_init();
|
|
shmobile_earlytimer_init();
|
|
sh73a0_register_twd();
|
|
}
|
|
|
|
void __init sh73a0_add_early_devices(void)
|
|
{
|
|
early_platform_add_devices(sh73a0_devices_dt,
|
|
ARRAY_SIZE(sh73a0_devices_dt));
|
|
early_platform_add_devices(sh73a0_early_devices,
|
|
ARRAY_SIZE(sh73a0_early_devices));
|
|
|
|
/* setup early console here as well */
|
|
shmobile_setup_console();
|
|
}
|
|
|
|
#ifdef CONFIG_USE_OF
|
|
|
|
void __init sh73a0_add_standard_devices_dt(void)
|
|
{
|
|
struct platform_device_info devinfo = { .name = "cpufreq-cpu0", .id = -1, };
|
|
|
|
/* clocks are setup late during boot in the case of DT */
|
|
sh73a0_clock_init();
|
|
|
|
platform_add_devices(sh73a0_devices_dt,
|
|
ARRAY_SIZE(sh73a0_devices_dt));
|
|
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
|
|
|
/* Instantiate cpufreq-cpu0 */
|
|
platform_device_register_full(&devinfo);
|
|
}
|
|
|
|
static const char *sh73a0_boards_compat_dt[] __initdata = {
|
|
"renesas,sh73a0",
|
|
NULL,
|
|
};
|
|
|
|
DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
|
|
.smp = smp_ops(sh73a0_smp_ops),
|
|
.map_io = sh73a0_map_io,
|
|
.init_early = sh73a0_init_delay,
|
|
.nr_irqs = NR_IRQS_LEGACY,
|
|
.init_machine = sh73a0_add_standard_devices_dt,
|
|
.dt_compat = sh73a0_boards_compat_dt,
|
|
MACHINE_END
|
|
#endif /* CONFIG_USE_OF */
|