![Feng Tang](/assets/img/avatar_default.png)
dw_spi driver in upstream only supports PIO mode, and this patch will support it to cowork with the Designware dma controller used on Intel Moorestown platform, at the same time it provides a general framework to support dw_spi core to cowork with dma controllers on other platforms It has been tested with a Option GTM501L 3G modem and Infenion 60x60 modem. To use DMA mode, DMA controller 2 of Moorestown has to be enabled Also change the dma interface suggested by Linus Walleij. Acked-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Feng Tang <feng.tang@intel.com> [Typo fix and renames to match intel_mid_dma renaming] Signed-off-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
234 lines
5.4 KiB
C
234 lines
5.4 KiB
C
#ifndef DW_SPI_HEADER_H
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#define DW_SPI_HEADER_H
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#include <linux/io.h>
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/* Bit fields in CTRLR0 */
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#define SPI_DFS_OFFSET 0
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#define SPI_FRF_OFFSET 4
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#define SPI_FRF_SPI 0x0
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#define SPI_FRF_SSP 0x1
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#define SPI_FRF_MICROWIRE 0x2
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#define SPI_FRF_RESV 0x3
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#define SPI_MODE_OFFSET 6
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#define SPI_SCPH_OFFSET 6
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#define SPI_SCOL_OFFSET 7
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#define SPI_TMOD_OFFSET 8
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#define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET)
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#define SPI_TMOD_TR 0x0 /* xmit & recv */
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#define SPI_TMOD_TO 0x1 /* xmit only */
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#define SPI_TMOD_RO 0x2 /* recv only */
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#define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */
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#define SPI_SLVOE_OFFSET 10
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#define SPI_SRL_OFFSET 11
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#define SPI_CFS_OFFSET 12
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/* Bit fields in SR, 7 bits */
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#define SR_MASK 0x7f /* cover 7 bits */
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#define SR_BUSY (1 << 0)
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#define SR_TF_NOT_FULL (1 << 1)
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#define SR_TF_EMPT (1 << 2)
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#define SR_RF_NOT_EMPT (1 << 3)
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#define SR_RF_FULL (1 << 4)
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#define SR_TX_ERR (1 << 5)
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#define SR_DCOL (1 << 6)
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/* Bit fields in ISR, IMR, RISR, 7 bits */
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#define SPI_INT_TXEI (1 << 0)
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#define SPI_INT_TXOI (1 << 1)
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#define SPI_INT_RXUI (1 << 2)
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#define SPI_INT_RXOI (1 << 3)
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#define SPI_INT_RXFI (1 << 4)
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#define SPI_INT_MSTI (1 << 5)
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/* TX RX interrupt level threshhold, max can be 256 */
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#define SPI_INT_THRESHOLD 32
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enum dw_ssi_type {
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SSI_MOTO_SPI = 0,
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SSI_TI_SSP,
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SSI_NS_MICROWIRE,
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};
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struct dw_spi_reg {
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u32 ctrl0;
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u32 ctrl1;
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u32 ssienr;
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u32 mwcr;
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u32 ser;
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u32 baudr;
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u32 txfltr;
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u32 rxfltr;
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u32 txflr;
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u32 rxflr;
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u32 sr;
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u32 imr;
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u32 isr;
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u32 risr;
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u32 txoicr;
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u32 rxoicr;
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u32 rxuicr;
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u32 msticr;
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u32 icr;
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u32 dmacr;
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u32 dmatdlr;
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u32 dmardlr;
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u32 idr;
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u32 version;
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u32 dr; /* Currently oper as 32 bits,
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though only low 16 bits matters */
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} __packed;
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struct dw_spi;
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struct dw_spi_dma_ops {
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int (*dma_init)(struct dw_spi *dws);
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void (*dma_exit)(struct dw_spi *dws);
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int (*dma_transfer)(struct dw_spi *dws, int cs_change);
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};
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struct dw_spi {
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struct spi_master *master;
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struct spi_device *cur_dev;
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struct device *parent_dev;
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enum dw_ssi_type type;
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void __iomem *regs;
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unsigned long paddr;
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u32 iolen;
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int irq;
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u32 fifo_len; /* depth of the FIFO buffer */
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u32 max_freq; /* max bus freq supported */
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u16 bus_num;
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u16 num_cs; /* supported slave numbers */
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/* Driver message queue */
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struct workqueue_struct *workqueue;
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struct work_struct pump_messages;
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spinlock_t lock;
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struct list_head queue;
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int busy;
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int run;
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/* Message Transfer pump */
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struct tasklet_struct pump_transfers;
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/* Current message transfer state info */
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struct spi_message *cur_msg;
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struct spi_transfer *cur_transfer;
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struct chip_data *cur_chip;
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struct chip_data *prev_chip;
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size_t len;
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void *tx;
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void *tx_end;
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void *rx;
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void *rx_end;
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int dma_mapped;
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dma_addr_t rx_dma;
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dma_addr_t tx_dma;
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size_t rx_map_len;
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size_t tx_map_len;
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u8 n_bytes; /* current is a 1/2 bytes op */
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u8 max_bits_per_word; /* maxim is 16b */
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u32 dma_width;
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int cs_change;
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int (*write)(struct dw_spi *dws);
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int (*read)(struct dw_spi *dws);
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irqreturn_t (*transfer_handler)(struct dw_spi *dws);
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void (*cs_control)(u32 command);
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/* Dma info */
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int dma_inited;
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struct dma_chan *txchan;
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struct scatterlist tx_sgl;
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struct dma_chan *rxchan;
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struct scatterlist rx_sgl;
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int dma_chan_done;
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struct device *dma_dev;
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dma_addr_t dma_addr; /* phy address of the Data register */
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struct dw_spi_dma_ops *dma_ops;
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void *dma_priv; /* platform relate info */
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struct pci_dev *dmac;
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/* Bus interface info */
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void *priv;
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#ifdef CONFIG_DEBUG_FS
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struct dentry *debugfs;
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#endif
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};
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#define dw_readl(dw, name) \
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__raw_readl(&(((struct dw_spi_reg *)dw->regs)->name))
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#define dw_writel(dw, name, val) \
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__raw_writel((val), &(((struct dw_spi_reg *)dw->regs)->name))
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#define dw_readw(dw, name) \
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__raw_readw(&(((struct dw_spi_reg *)dw->regs)->name))
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#define dw_writew(dw, name, val) \
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__raw_writew((val), &(((struct dw_spi_reg *)dw->regs)->name))
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static inline void spi_enable_chip(struct dw_spi *dws, int enable)
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{
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dw_writel(dws, ssienr, (enable ? 1 : 0));
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}
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static inline void spi_set_clk(struct dw_spi *dws, u16 div)
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{
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dw_writel(dws, baudr, div);
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}
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static inline void spi_chip_sel(struct dw_spi *dws, u16 cs)
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{
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if (cs > dws->num_cs)
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return;
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if (dws->cs_control)
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dws->cs_control(1);
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dw_writel(dws, ser, 1 << cs);
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}
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/* Disable IRQ bits */
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static inline void spi_mask_intr(struct dw_spi *dws, u32 mask)
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{
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u32 new_mask;
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new_mask = dw_readl(dws, imr) & ~mask;
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dw_writel(dws, imr, new_mask);
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}
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/* Enable IRQ bits */
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static inline void spi_umask_intr(struct dw_spi *dws, u32 mask)
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{
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u32 new_mask;
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new_mask = dw_readl(dws, imr) | mask;
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dw_writel(dws, imr, new_mask);
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}
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/*
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* Each SPI slave device to work with dw_api controller should
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* has such a structure claiming its working mode (PIO/DMA etc),
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* which can be save in the "controller_data" member of the
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* struct spi_device
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*/
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struct dw_spi_chip {
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u8 poll_mode; /* 0 for contoller polling mode */
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u8 type; /* SPI/SSP/Micrwire */
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u8 enable_dma;
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void (*cs_control)(u32 command);
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};
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extern int dw_spi_add_host(struct dw_spi *dws);
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extern void dw_spi_remove_host(struct dw_spi *dws);
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extern int dw_spi_suspend_host(struct dw_spi *dws);
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extern int dw_spi_resume_host(struct dw_spi *dws);
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extern void dw_spi_xfer_done(struct dw_spi *dws);
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/* platform related setup */
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extern int dw_spi_mid_init(struct dw_spi *dws); /* Intel MID platforms */
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#endif /* DW_SPI_HEADER_H */
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