![Lyude Paul](/assets/img/avatar_default.png)
Since it seems that some vendors are storing the ATIF ACPI methods under the same handle that ATPX lives under instead of the device's own handle, we're going to need to be able to retrieve this handle later so we can probe for ATIF there. Signed-off-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
673 lines
17 KiB
C
673 lines
17 KiB
C
/*
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* Copyright (c) 2010 Red Hat Inc.
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* Author : Dave Airlie <airlied@redhat.com>
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*
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* Licensed under GPLv2
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*
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* ATPX support for both Intel/ATI
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*/
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#include <linux/vga_switcheroo.h>
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#include <linux/slab.h>
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#include <linux/acpi.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include "amd_acpi.h"
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#define AMDGPU_PX_QUIRK_FORCE_ATPX (1 << 0)
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struct amdgpu_px_quirk {
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u32 chip_vendor;
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u32 chip_device;
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u32 subsys_vendor;
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u32 subsys_device;
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u32 px_quirk_flags;
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};
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struct amdgpu_atpx_functions {
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bool px_params;
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bool power_cntl;
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bool disp_mux_cntl;
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bool i2c_mux_cntl;
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bool switch_start;
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bool switch_end;
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bool disp_connectors_mapping;
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bool disp_detection_ports;
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};
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struct amdgpu_atpx {
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acpi_handle handle;
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struct amdgpu_atpx_functions functions;
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bool is_hybrid;
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bool dgpu_req_power_for_displays;
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};
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static struct amdgpu_atpx_priv {
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bool atpx_detected;
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bool bridge_pm_usable;
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unsigned int quirks;
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/* handle for device - and atpx */
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acpi_handle dhandle;
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acpi_handle other_handle;
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struct amdgpu_atpx atpx;
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} amdgpu_atpx_priv;
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struct atpx_verify_interface {
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u16 size; /* structure size in bytes (includes size field) */
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u16 version; /* version */
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u32 function_bits; /* supported functions bit vector */
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} __packed;
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struct atpx_px_params {
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u16 size; /* structure size in bytes (includes size field) */
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u32 valid_flags; /* which flags are valid */
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u32 flags; /* flags */
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} __packed;
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struct atpx_power_control {
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u16 size;
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u8 dgpu_state;
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} __packed;
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struct atpx_mux {
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u16 size;
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u16 mux;
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} __packed;
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bool amdgpu_has_atpx(void) {
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return amdgpu_atpx_priv.atpx_detected;
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}
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bool amdgpu_has_atpx_dgpu_power_cntl(void) {
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return amdgpu_atpx_priv.atpx.functions.power_cntl;
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}
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bool amdgpu_is_atpx_hybrid(void) {
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return amdgpu_atpx_priv.atpx.is_hybrid;
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}
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bool amdgpu_atpx_dgpu_req_power_for_displays(void) {
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return amdgpu_atpx_priv.atpx.dgpu_req_power_for_displays;
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}
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#if defined(CONFIG_ACPI)
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void *amdgpu_atpx_get_dhandle(void) {
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return amdgpu_atpx_priv.dhandle;
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}
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#endif
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/**
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* amdgpu_atpx_call - call an ATPX method
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*
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* @handle: acpi handle
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* @function: the ATPX function to execute
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* @params: ATPX function params
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*
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* Executes the requested ATPX function (all asics).
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* Returns a pointer to the acpi output buffer.
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*/
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static union acpi_object *amdgpu_atpx_call(acpi_handle handle, int function,
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struct acpi_buffer *params)
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{
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acpi_status status;
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union acpi_object atpx_arg_elements[2];
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struct acpi_object_list atpx_arg;
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struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
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atpx_arg.count = 2;
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atpx_arg.pointer = &atpx_arg_elements[0];
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atpx_arg_elements[0].type = ACPI_TYPE_INTEGER;
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atpx_arg_elements[0].integer.value = function;
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if (params) {
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atpx_arg_elements[1].type = ACPI_TYPE_BUFFER;
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atpx_arg_elements[1].buffer.length = params->length;
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atpx_arg_elements[1].buffer.pointer = params->pointer;
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} else {
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/* We need a second fake parameter */
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atpx_arg_elements[1].type = ACPI_TYPE_INTEGER;
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atpx_arg_elements[1].integer.value = 0;
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}
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status = acpi_evaluate_object(handle, NULL, &atpx_arg, &buffer);
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/* Fail only if calling the method fails and ATPX is supported */
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if (ACPI_FAILURE(status) && status != AE_NOT_FOUND) {
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printk("failed to evaluate ATPX got %s\n",
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acpi_format_exception(status));
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kfree(buffer.pointer);
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return NULL;
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}
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return buffer.pointer;
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}
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/**
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* amdgpu_atpx_parse_functions - parse supported functions
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*
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* @f: supported functions struct
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* @mask: supported functions mask from ATPX
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*
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* Use the supported functions mask from ATPX function
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* ATPX_FUNCTION_VERIFY_INTERFACE to determine what functions
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* are supported (all asics).
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*/
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static void amdgpu_atpx_parse_functions(struct amdgpu_atpx_functions *f, u32 mask)
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{
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f->px_params = mask & ATPX_GET_PX_PARAMETERS_SUPPORTED;
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f->power_cntl = mask & ATPX_POWER_CONTROL_SUPPORTED;
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f->disp_mux_cntl = mask & ATPX_DISPLAY_MUX_CONTROL_SUPPORTED;
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f->i2c_mux_cntl = mask & ATPX_I2C_MUX_CONTROL_SUPPORTED;
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f->switch_start = mask & ATPX_GRAPHICS_DEVICE_SWITCH_START_NOTIFICATION_SUPPORTED;
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f->switch_end = mask & ATPX_GRAPHICS_DEVICE_SWITCH_END_NOTIFICATION_SUPPORTED;
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f->disp_connectors_mapping = mask & ATPX_GET_DISPLAY_CONNECTORS_MAPPING_SUPPORTED;
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f->disp_detection_ports = mask & ATPX_GET_DISPLAY_DETECTION_PORTS_SUPPORTED;
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}
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/**
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* amdgpu_atpx_validate_functions - validate ATPX functions
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*
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* @atpx: amdgpu atpx struct
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*
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* Validate that required functions are enabled (all asics).
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* returns 0 on success, error on failure.
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*/
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static int amdgpu_atpx_validate(struct amdgpu_atpx *atpx)
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{
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u32 valid_bits = 0;
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if (atpx->functions.px_params) {
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union acpi_object *info;
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struct atpx_px_params output;
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size_t size;
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info = amdgpu_atpx_call(atpx->handle, ATPX_FUNCTION_GET_PX_PARAMETERS, NULL);
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if (!info)
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return -EIO;
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memset(&output, 0, sizeof(output));
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size = *(u16 *) info->buffer.pointer;
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if (size < 10) {
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printk("ATPX buffer is too small: %zu\n", size);
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kfree(info);
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return -EINVAL;
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}
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size = min(sizeof(output), size);
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memcpy(&output, info->buffer.pointer, size);
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valid_bits = output.flags & output.valid_flags;
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kfree(info);
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}
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/* if separate mux flag is set, mux controls are required */
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if (valid_bits & ATPX_SEPARATE_MUX_FOR_I2C) {
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atpx->functions.i2c_mux_cntl = true;
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atpx->functions.disp_mux_cntl = true;
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}
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/* if any outputs are muxed, mux controls are required */
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if (valid_bits & (ATPX_CRT1_RGB_SIGNAL_MUXED |
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ATPX_TV_SIGNAL_MUXED |
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ATPX_DFP_SIGNAL_MUXED))
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atpx->functions.disp_mux_cntl = true;
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/* some bioses set these bits rather than flagging power_cntl as supported */
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if (valid_bits & (ATPX_DYNAMIC_PX_SUPPORTED |
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ATPX_DYNAMIC_DGPU_POWER_OFF_SUPPORTED))
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atpx->functions.power_cntl = true;
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atpx->is_hybrid = false;
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if (valid_bits & ATPX_MS_HYBRID_GFX_SUPPORTED) {
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if (amdgpu_atpx_priv.quirks & AMDGPU_PX_QUIRK_FORCE_ATPX) {
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printk("ATPX Hybrid Graphics, forcing to ATPX\n");
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atpx->functions.power_cntl = true;
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atpx->is_hybrid = false;
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} else {
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printk("ATPX Hybrid Graphics\n");
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/*
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* Disable legacy PM methods only when pcie port PM is usable,
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* otherwise the device might fail to power off or power on.
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*/
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atpx->functions.power_cntl = !amdgpu_atpx_priv.bridge_pm_usable;
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atpx->is_hybrid = true;
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}
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}
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atpx->dgpu_req_power_for_displays = false;
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if (valid_bits & ATPX_DGPU_REQ_POWER_FOR_DISPLAYS)
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atpx->dgpu_req_power_for_displays = true;
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return 0;
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}
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/**
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* amdgpu_atpx_verify_interface - verify ATPX
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*
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* @atpx: amdgpu atpx struct
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*
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* Execute the ATPX_FUNCTION_VERIFY_INTERFACE ATPX function
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* to initialize ATPX and determine what features are supported
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* (all asics).
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* returns 0 on success, error on failure.
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*/
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static int amdgpu_atpx_verify_interface(struct amdgpu_atpx *atpx)
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{
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union acpi_object *info;
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struct atpx_verify_interface output;
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size_t size;
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int err = 0;
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info = amdgpu_atpx_call(atpx->handle, ATPX_FUNCTION_VERIFY_INTERFACE, NULL);
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if (!info)
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return -EIO;
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memset(&output, 0, sizeof(output));
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size = *(u16 *) info->buffer.pointer;
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if (size < 8) {
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printk("ATPX buffer is too small: %zu\n", size);
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err = -EINVAL;
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goto out;
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}
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size = min(sizeof(output), size);
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memcpy(&output, info->buffer.pointer, size);
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/* TODO: check version? */
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printk("ATPX version %u, functions 0x%08x\n",
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output.version, output.function_bits);
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amdgpu_atpx_parse_functions(&atpx->functions, output.function_bits);
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out:
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kfree(info);
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return err;
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}
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/**
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* amdgpu_atpx_set_discrete_state - power up/down discrete GPU
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*
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* @atpx: atpx info struct
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* @state: discrete GPU state (0 = power down, 1 = power up)
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*
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* Execute the ATPX_FUNCTION_POWER_CONTROL ATPX function to
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* power down/up the discrete GPU (all asics).
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* Returns 0 on success, error on failure.
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*/
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static int amdgpu_atpx_set_discrete_state(struct amdgpu_atpx *atpx, u8 state)
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{
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struct acpi_buffer params;
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union acpi_object *info;
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struct atpx_power_control input;
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if (atpx->functions.power_cntl) {
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input.size = 3;
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input.dgpu_state = state;
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params.length = input.size;
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params.pointer = &input;
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info = amdgpu_atpx_call(atpx->handle,
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ATPX_FUNCTION_POWER_CONTROL,
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¶ms);
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if (!info)
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return -EIO;
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kfree(info);
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/* 200ms delay is required after off */
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if (state == 0)
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msleep(200);
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}
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return 0;
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}
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/**
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* amdgpu_atpx_switch_disp_mux - switch display mux
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*
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* @atpx: atpx info struct
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* @mux_id: mux state (0 = integrated GPU, 1 = discrete GPU)
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*
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* Execute the ATPX_FUNCTION_DISPLAY_MUX_CONTROL ATPX function to
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* switch the display mux between the discrete GPU and integrated GPU
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* (all asics).
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* Returns 0 on success, error on failure.
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*/
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static int amdgpu_atpx_switch_disp_mux(struct amdgpu_atpx *atpx, u16 mux_id)
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{
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struct acpi_buffer params;
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union acpi_object *info;
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struct atpx_mux input;
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if (atpx->functions.disp_mux_cntl) {
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input.size = 4;
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input.mux = mux_id;
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params.length = input.size;
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params.pointer = &input;
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info = amdgpu_atpx_call(atpx->handle,
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ATPX_FUNCTION_DISPLAY_MUX_CONTROL,
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¶ms);
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if (!info)
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return -EIO;
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kfree(info);
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}
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return 0;
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}
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/**
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* amdgpu_atpx_switch_i2c_mux - switch i2c/hpd mux
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*
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* @atpx: atpx info struct
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* @mux_id: mux state (0 = integrated GPU, 1 = discrete GPU)
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*
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* Execute the ATPX_FUNCTION_I2C_MUX_CONTROL ATPX function to
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* switch the i2c/hpd mux between the discrete GPU and integrated GPU
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* (all asics).
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* Returns 0 on success, error on failure.
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*/
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static int amdgpu_atpx_switch_i2c_mux(struct amdgpu_atpx *atpx, u16 mux_id)
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{
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struct acpi_buffer params;
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union acpi_object *info;
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struct atpx_mux input;
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if (atpx->functions.i2c_mux_cntl) {
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input.size = 4;
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input.mux = mux_id;
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params.length = input.size;
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params.pointer = &input;
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info = amdgpu_atpx_call(atpx->handle,
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ATPX_FUNCTION_I2C_MUX_CONTROL,
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¶ms);
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if (!info)
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return -EIO;
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kfree(info);
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}
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return 0;
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}
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/**
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* amdgpu_atpx_switch_start - notify the sbios of a GPU switch
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*
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* @atpx: atpx info struct
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* @mux_id: mux state (0 = integrated GPU, 1 = discrete GPU)
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*
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* Execute the ATPX_FUNCTION_GRAPHICS_DEVICE_SWITCH_START_NOTIFICATION ATPX
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* function to notify the sbios that a switch between the discrete GPU and
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* integrated GPU has begun (all asics).
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* Returns 0 on success, error on failure.
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*/
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static int amdgpu_atpx_switch_start(struct amdgpu_atpx *atpx, u16 mux_id)
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{
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struct acpi_buffer params;
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union acpi_object *info;
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struct atpx_mux input;
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if (atpx->functions.switch_start) {
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input.size = 4;
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input.mux = mux_id;
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params.length = input.size;
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params.pointer = &input;
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info = amdgpu_atpx_call(atpx->handle,
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ATPX_FUNCTION_GRAPHICS_DEVICE_SWITCH_START_NOTIFICATION,
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¶ms);
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if (!info)
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return -EIO;
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kfree(info);
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}
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return 0;
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}
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/**
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* amdgpu_atpx_switch_end - notify the sbios of a GPU switch
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*
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* @atpx: atpx info struct
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* @mux_id: mux state (0 = integrated GPU, 1 = discrete GPU)
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*
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* Execute the ATPX_FUNCTION_GRAPHICS_DEVICE_SWITCH_END_NOTIFICATION ATPX
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* function to notify the sbios that a switch between the discrete GPU and
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* integrated GPU has ended (all asics).
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* Returns 0 on success, error on failure.
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*/
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static int amdgpu_atpx_switch_end(struct amdgpu_atpx *atpx, u16 mux_id)
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{
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struct acpi_buffer params;
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union acpi_object *info;
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struct atpx_mux input;
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if (atpx->functions.switch_end) {
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input.size = 4;
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input.mux = mux_id;
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params.length = input.size;
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params.pointer = &input;
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info = amdgpu_atpx_call(atpx->handle,
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ATPX_FUNCTION_GRAPHICS_DEVICE_SWITCH_END_NOTIFICATION,
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¶ms);
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if (!info)
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return -EIO;
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kfree(info);
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}
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return 0;
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}
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/**
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* amdgpu_atpx_switchto - switch to the requested GPU
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*
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* @id: GPU to switch to
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*
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* Execute the necessary ATPX functions to switch between the discrete GPU and
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* integrated GPU (all asics).
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* Returns 0 on success, error on failure.
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*/
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static int amdgpu_atpx_switchto(enum vga_switcheroo_client_id id)
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{
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u16 gpu_id;
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if (id == VGA_SWITCHEROO_IGD)
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gpu_id = ATPX_INTEGRATED_GPU;
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else
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gpu_id = ATPX_DISCRETE_GPU;
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amdgpu_atpx_switch_start(&amdgpu_atpx_priv.atpx, gpu_id);
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amdgpu_atpx_switch_disp_mux(&amdgpu_atpx_priv.atpx, gpu_id);
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amdgpu_atpx_switch_i2c_mux(&amdgpu_atpx_priv.atpx, gpu_id);
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amdgpu_atpx_switch_end(&amdgpu_atpx_priv.atpx, gpu_id);
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return 0;
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}
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/**
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* amdgpu_atpx_power_state - power down/up the requested GPU
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*
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* @id: GPU to power down/up
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* @state: requested power state (0 = off, 1 = on)
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*
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* Execute the necessary ATPX function to power down/up the discrete GPU
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* (all asics).
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* Returns 0 on success, error on failure.
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*/
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static int amdgpu_atpx_power_state(enum vga_switcheroo_client_id id,
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enum vga_switcheroo_state state)
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{
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/* on w500 ACPI can't change intel gpu state */
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if (id == VGA_SWITCHEROO_IGD)
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return 0;
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amdgpu_atpx_set_discrete_state(&amdgpu_atpx_priv.atpx, state);
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return 0;
|
|
}
|
|
|
|
/**
|
|
* amdgpu_atpx_pci_probe_handle - look up the ATPX handle
|
|
*
|
|
* @pdev: pci device
|
|
*
|
|
* Look up the ATPX handles (all asics).
|
|
* Returns true if the handles are found, false if not.
|
|
*/
|
|
static bool amdgpu_atpx_pci_probe_handle(struct pci_dev *pdev)
|
|
{
|
|
acpi_handle dhandle, atpx_handle;
|
|
acpi_status status;
|
|
|
|
dhandle = ACPI_HANDLE(&pdev->dev);
|
|
if (!dhandle)
|
|
return false;
|
|
|
|
status = acpi_get_handle(dhandle, "ATPX", &atpx_handle);
|
|
if (ACPI_FAILURE(status)) {
|
|
amdgpu_atpx_priv.other_handle = dhandle;
|
|
return false;
|
|
}
|
|
amdgpu_atpx_priv.dhandle = dhandle;
|
|
amdgpu_atpx_priv.atpx.handle = atpx_handle;
|
|
return true;
|
|
}
|
|
|
|
/**
|
|
* amdgpu_atpx_init - verify the ATPX interface
|
|
*
|
|
* Verify the ATPX interface (all asics).
|
|
* Returns 0 on success, error on failure.
|
|
*/
|
|
static int amdgpu_atpx_init(void)
|
|
{
|
|
int r;
|
|
|
|
/* set up the ATPX handle */
|
|
r = amdgpu_atpx_verify_interface(&amdgpu_atpx_priv.atpx);
|
|
if (r)
|
|
return r;
|
|
|
|
/* validate the atpx setup */
|
|
r = amdgpu_atpx_validate(&amdgpu_atpx_priv.atpx);
|
|
if (r)
|
|
return r;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* amdgpu_atpx_get_client_id - get the client id
|
|
*
|
|
* @pdev: pci device
|
|
*
|
|
* look up whether we are the integrated or discrete GPU (all asics).
|
|
* Returns the client id.
|
|
*/
|
|
static enum vga_switcheroo_client_id amdgpu_atpx_get_client_id(struct pci_dev *pdev)
|
|
{
|
|
if (amdgpu_atpx_priv.dhandle == ACPI_HANDLE(&pdev->dev))
|
|
return VGA_SWITCHEROO_IGD;
|
|
else
|
|
return VGA_SWITCHEROO_DIS;
|
|
}
|
|
|
|
static const struct vga_switcheroo_handler amdgpu_atpx_handler = {
|
|
.switchto = amdgpu_atpx_switchto,
|
|
.power_state = amdgpu_atpx_power_state,
|
|
.get_client_id = amdgpu_atpx_get_client_id,
|
|
};
|
|
|
|
static const struct amdgpu_px_quirk amdgpu_px_quirk_list[] = {
|
|
/* HG _PR3 doesn't seem to work on this A+A weston board */
|
|
{ 0x1002, 0x6900, 0x1002, 0x0124, AMDGPU_PX_QUIRK_FORCE_ATPX },
|
|
{ 0x1002, 0x6900, 0x1028, 0x0812, AMDGPU_PX_QUIRK_FORCE_ATPX },
|
|
{ 0x1002, 0x6900, 0x1028, 0x0813, AMDGPU_PX_QUIRK_FORCE_ATPX },
|
|
{ 0, 0, 0, 0, 0 },
|
|
};
|
|
|
|
static void amdgpu_atpx_get_quirks(struct pci_dev *pdev)
|
|
{
|
|
const struct amdgpu_px_quirk *p = amdgpu_px_quirk_list;
|
|
|
|
/* Apply PX quirks */
|
|
while (p && p->chip_device != 0) {
|
|
if (pdev->vendor == p->chip_vendor &&
|
|
pdev->device == p->chip_device &&
|
|
pdev->subsystem_vendor == p->subsys_vendor &&
|
|
pdev->subsystem_device == p->subsys_device) {
|
|
amdgpu_atpx_priv.quirks |= p->px_quirk_flags;
|
|
break;
|
|
}
|
|
++p;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* amdgpu_atpx_detect - detect whether we have PX
|
|
*
|
|
* Check if we have a PX system (all asics).
|
|
* Returns true if we have a PX system, false if not.
|
|
*/
|
|
static bool amdgpu_atpx_detect(void)
|
|
{
|
|
char acpi_method_name[255] = { 0 };
|
|
struct acpi_buffer buffer = {sizeof(acpi_method_name), acpi_method_name};
|
|
struct pci_dev *pdev = NULL;
|
|
bool has_atpx = false;
|
|
int vga_count = 0;
|
|
bool d3_supported = false;
|
|
struct pci_dev *parent_pdev;
|
|
|
|
while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
|
|
vga_count++;
|
|
|
|
has_atpx |= (amdgpu_atpx_pci_probe_handle(pdev) == true);
|
|
|
|
parent_pdev = pci_upstream_bridge(pdev);
|
|
d3_supported |= parent_pdev && parent_pdev->bridge_d3;
|
|
amdgpu_atpx_get_quirks(pdev);
|
|
}
|
|
|
|
while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
|
|
vga_count++;
|
|
|
|
has_atpx |= (amdgpu_atpx_pci_probe_handle(pdev) == true);
|
|
|
|
parent_pdev = pci_upstream_bridge(pdev);
|
|
d3_supported |= parent_pdev && parent_pdev->bridge_d3;
|
|
amdgpu_atpx_get_quirks(pdev);
|
|
}
|
|
|
|
if (has_atpx && vga_count == 2) {
|
|
acpi_get_name(amdgpu_atpx_priv.atpx.handle, ACPI_FULL_PATHNAME, &buffer);
|
|
pr_info("vga_switcheroo: detected switching method %s handle\n",
|
|
acpi_method_name);
|
|
amdgpu_atpx_priv.atpx_detected = true;
|
|
amdgpu_atpx_priv.bridge_pm_usable = d3_supported;
|
|
amdgpu_atpx_init();
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
/**
|
|
* amdgpu_register_atpx_handler - register with vga_switcheroo
|
|
*
|
|
* Register the PX callbacks with vga_switcheroo (all asics).
|
|
*/
|
|
void amdgpu_register_atpx_handler(void)
|
|
{
|
|
bool r;
|
|
enum vga_switcheroo_handler_flags_t handler_flags = 0;
|
|
|
|
/* detect if we have any ATPX + 2 VGA in the system */
|
|
r = amdgpu_atpx_detect();
|
|
if (!r)
|
|
return;
|
|
|
|
vga_switcheroo_register_handler(&amdgpu_atpx_handler, handler_flags);
|
|
}
|
|
|
|
/**
|
|
* amdgpu_unregister_atpx_handler - unregister with vga_switcheroo
|
|
*
|
|
* Unregister the PX callbacks with vga_switcheroo (all asics).
|
|
*/
|
|
void amdgpu_unregister_atpx_handler(void)
|
|
{
|
|
vga_switcheroo_unregister_handler();
|
|
}
|