![Huang Rui](/assets/img/avatar_default.png)
We still use legacy type of gem_object_create, it should update to ttm_bo_type now. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
891 lines
23 KiB
C
891 lines
23 KiB
C
/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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#include <linux/ktime.h>
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#include <linux/pagemap.h>
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#include <drm/drmP.h>
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#include <drm/amdgpu_drm.h>
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#include "amdgpu.h"
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#include "amdgpu_display.h"
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void amdgpu_gem_object_free(struct drm_gem_object *gobj)
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{
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struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj);
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if (robj) {
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amdgpu_mn_unregister(robj);
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amdgpu_bo_unref(&robj);
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}
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}
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int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
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int alignment, u32 initial_domain,
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u64 flags, enum ttm_bo_type type,
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struct reservation_object *resv,
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struct drm_gem_object **obj)
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{
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struct amdgpu_bo *bo;
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struct amdgpu_bo_param bp;
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int r;
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memset(&bp, 0, sizeof(bp));
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*obj = NULL;
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/* At least align on page size */
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if (alignment < PAGE_SIZE) {
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alignment = PAGE_SIZE;
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}
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bp.size = size;
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bp.byte_align = alignment;
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bp.type = type;
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bp.resv = resv;
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bp.preferred_domain = initial_domain;
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retry:
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bp.flags = flags;
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bp.domain = initial_domain;
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r = amdgpu_bo_create(adev, &bp, &bo);
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if (r) {
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if (r != -ERESTARTSYS) {
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if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {
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flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
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goto retry;
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}
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if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
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initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
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goto retry;
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}
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DRM_DEBUG("Failed to allocate GEM object (%ld, %d, %u, %d)\n",
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size, initial_domain, alignment, r);
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}
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return r;
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}
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*obj = &bo->gem_base;
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return 0;
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}
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void amdgpu_gem_force_release(struct amdgpu_device *adev)
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{
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struct drm_device *ddev = adev->ddev;
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struct drm_file *file;
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mutex_lock(&ddev->filelist_mutex);
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list_for_each_entry(file, &ddev->filelist, lhead) {
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struct drm_gem_object *gobj;
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int handle;
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WARN_ONCE(1, "Still active user space clients!\n");
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spin_lock(&file->table_lock);
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idr_for_each_entry(&file->object_idr, gobj, handle) {
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WARN_ONCE(1, "And also active allocations!\n");
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drm_gem_object_put_unlocked(gobj);
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}
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idr_destroy(&file->object_idr);
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spin_unlock(&file->table_lock);
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}
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mutex_unlock(&ddev->filelist_mutex);
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}
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/*
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* Call from drm_gem_handle_create which appear in both new and open ioctl
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* case.
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*/
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int amdgpu_gem_object_open(struct drm_gem_object *obj,
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struct drm_file *file_priv)
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{
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struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj);
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struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
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struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
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struct amdgpu_vm *vm = &fpriv->vm;
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struct amdgpu_bo_va *bo_va;
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struct mm_struct *mm;
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int r;
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mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm);
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if (mm && mm != current->mm)
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return -EPERM;
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if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID &&
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abo->tbo.resv != vm->root.base.bo->tbo.resv)
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return -EPERM;
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r = amdgpu_bo_reserve(abo, false);
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if (r)
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return r;
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bo_va = amdgpu_vm_bo_find(vm, abo);
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if (!bo_va) {
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bo_va = amdgpu_vm_bo_add(adev, vm, abo);
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} else {
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++bo_va->ref_count;
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}
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amdgpu_bo_unreserve(abo);
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return 0;
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}
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void amdgpu_gem_object_close(struct drm_gem_object *obj,
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struct drm_file *file_priv)
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{
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struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
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struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
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struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
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struct amdgpu_vm *vm = &fpriv->vm;
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struct amdgpu_bo_list_entry vm_pd;
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struct list_head list, duplicates;
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struct ttm_validate_buffer tv;
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struct ww_acquire_ctx ticket;
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struct amdgpu_bo_va *bo_va;
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int r;
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INIT_LIST_HEAD(&list);
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INIT_LIST_HEAD(&duplicates);
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tv.bo = &bo->tbo;
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tv.shared = true;
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list_add(&tv.head, &list);
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amdgpu_vm_get_pd_bo(vm, &list, &vm_pd);
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r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates);
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if (r) {
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dev_err(adev->dev, "leaking bo va because "
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"we fail to reserve bo (%d)\n", r);
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return;
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}
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bo_va = amdgpu_vm_bo_find(vm, bo);
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if (bo_va && --bo_va->ref_count == 0) {
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amdgpu_vm_bo_rmv(adev, bo_va);
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if (amdgpu_vm_ready(vm)) {
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struct dma_fence *fence = NULL;
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r = amdgpu_vm_clear_freed(adev, vm, &fence);
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if (unlikely(r)) {
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dev_err(adev->dev, "failed to clear page "
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"tables on GEM object close (%d)\n", r);
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}
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if (fence) {
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amdgpu_bo_fence(bo, fence, true);
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dma_fence_put(fence);
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}
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}
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}
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ttm_eu_backoff_reservation(&ticket, &list);
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}
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/*
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* GEM ioctls.
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*/
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int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
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struct drm_file *filp)
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{
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struct amdgpu_device *adev = dev->dev_private;
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struct amdgpu_fpriv *fpriv = filp->driver_priv;
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struct amdgpu_vm *vm = &fpriv->vm;
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union drm_amdgpu_gem_create *args = data;
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uint64_t flags = args->in.domain_flags;
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uint64_t size = args->in.bo_size;
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struct reservation_object *resv = NULL;
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struct drm_gem_object *gobj;
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uint32_t handle;
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int r;
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/* reject invalid gem flags */
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if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
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AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
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AMDGPU_GEM_CREATE_CPU_GTT_USWC |
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AMDGPU_GEM_CREATE_VRAM_CLEARED |
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AMDGPU_GEM_CREATE_VM_ALWAYS_VALID |
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AMDGPU_GEM_CREATE_EXPLICIT_SYNC))
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return -EINVAL;
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/* reject invalid gem domains */
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if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK)
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return -EINVAL;
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/* create a gem object to contain this object in */
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if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
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AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
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if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
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/* if gds bo is created from user space, it must be
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* passed to bo list
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*/
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DRM_ERROR("GDS bo cannot be per-vm-bo\n");
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return -EINVAL;
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}
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flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
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if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS)
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size = size << AMDGPU_GDS_SHIFT;
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else if (args->in.domains == AMDGPU_GEM_DOMAIN_GWS)
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size = size << AMDGPU_GWS_SHIFT;
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else if (args->in.domains == AMDGPU_GEM_DOMAIN_OA)
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size = size << AMDGPU_OA_SHIFT;
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else
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return -EINVAL;
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}
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size = roundup(size, PAGE_SIZE);
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if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
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r = amdgpu_bo_reserve(vm->root.base.bo, false);
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if (r)
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return r;
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resv = vm->root.base.bo->tbo.resv;
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}
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r = amdgpu_gem_object_create(adev, size, args->in.alignment,
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(u32)(0xffffffff & args->in.domains),
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flags, ttm_bo_type_device, resv, &gobj);
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if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
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if (!r) {
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struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
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abo->parent = amdgpu_bo_ref(vm->root.base.bo);
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}
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amdgpu_bo_unreserve(vm->root.base.bo);
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}
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if (r)
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return r;
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r = drm_gem_handle_create(filp, gobj, &handle);
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/* drop reference from allocate - handle holds it now */
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drm_gem_object_put_unlocked(gobj);
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if (r)
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return r;
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memset(args, 0, sizeof(*args));
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args->out.handle = handle;
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return 0;
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}
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int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
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struct drm_file *filp)
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{
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struct ttm_operation_ctx ctx = { true, false };
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struct amdgpu_device *adev = dev->dev_private;
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struct drm_amdgpu_gem_userptr *args = data;
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struct drm_gem_object *gobj;
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struct amdgpu_bo *bo;
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uint32_t handle;
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int r;
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if (offset_in_page(args->addr | args->size))
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return -EINVAL;
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/* reject unknown flag values */
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if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY |
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AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE |
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AMDGPU_GEM_USERPTR_REGISTER))
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return -EINVAL;
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if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) &&
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!(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) {
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/* if we want to write to it we must install a MMU notifier */
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return -EACCES;
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}
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/* create a gem object to contain this object in */
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r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU,
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0, ttm_bo_type_device, NULL, &gobj);
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if (r)
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return r;
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bo = gem_to_amdgpu_bo(gobj);
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bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
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bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
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r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags);
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if (r)
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goto release_object;
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if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) {
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r = amdgpu_mn_register(bo, args->addr);
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if (r)
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goto release_object;
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}
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if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
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r = amdgpu_ttm_tt_get_user_pages(bo->tbo.ttm,
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bo->tbo.ttm->pages);
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if (r)
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goto release_object;
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r = amdgpu_bo_reserve(bo, true);
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if (r)
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goto free_pages;
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amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
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r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
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amdgpu_bo_unreserve(bo);
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if (r)
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goto free_pages;
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}
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r = drm_gem_handle_create(filp, gobj, &handle);
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/* drop reference from allocate - handle holds it now */
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drm_gem_object_put_unlocked(gobj);
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if (r)
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return r;
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args->handle = handle;
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return 0;
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free_pages:
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release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages);
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release_object:
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drm_gem_object_put_unlocked(gobj);
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return r;
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}
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int amdgpu_mode_dumb_mmap(struct drm_file *filp,
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struct drm_device *dev,
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uint32_t handle, uint64_t *offset_p)
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{
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struct drm_gem_object *gobj;
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struct amdgpu_bo *robj;
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gobj = drm_gem_object_lookup(filp, handle);
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if (gobj == NULL) {
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return -ENOENT;
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}
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robj = gem_to_amdgpu_bo(gobj);
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if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) ||
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(robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
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drm_gem_object_put_unlocked(gobj);
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return -EPERM;
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}
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*offset_p = amdgpu_bo_mmap_offset(robj);
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drm_gem_object_put_unlocked(gobj);
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return 0;
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}
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int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
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struct drm_file *filp)
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{
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union drm_amdgpu_gem_mmap *args = data;
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uint32_t handle = args->in.handle;
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memset(args, 0, sizeof(*args));
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return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr);
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}
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/**
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* amdgpu_gem_timeout - calculate jiffies timeout from absolute value
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*
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* @timeout_ns: timeout in ns
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*
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* Calculate the timeout in jiffies from an absolute timeout in ns.
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*/
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unsigned long amdgpu_gem_timeout(uint64_t timeout_ns)
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{
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unsigned long timeout_jiffies;
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ktime_t timeout;
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/* clamp timeout if it's to large */
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if (((int64_t)timeout_ns) < 0)
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return MAX_SCHEDULE_TIMEOUT;
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timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get());
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if (ktime_to_ns(timeout) < 0)
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return 0;
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timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout));
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/* clamp timeout to avoid unsigned-> signed overflow */
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if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT )
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return MAX_SCHEDULE_TIMEOUT - 1;
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return timeout_jiffies;
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}
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int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
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struct drm_file *filp)
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{
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union drm_amdgpu_gem_wait_idle *args = data;
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struct drm_gem_object *gobj;
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struct amdgpu_bo *robj;
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uint32_t handle = args->in.handle;
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unsigned long timeout = amdgpu_gem_timeout(args->in.timeout);
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int r = 0;
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long ret;
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gobj = drm_gem_object_lookup(filp, handle);
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if (gobj == NULL) {
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return -ENOENT;
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}
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robj = gem_to_amdgpu_bo(gobj);
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ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true,
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timeout);
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/* ret == 0 means not signaled,
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* ret > 0 means signaled
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* ret < 0 means interrupted before timeout
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*/
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if (ret >= 0) {
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memset(args, 0, sizeof(*args));
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args->out.status = (ret == 0);
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} else
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r = ret;
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drm_gem_object_put_unlocked(gobj);
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return r;
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}
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int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
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struct drm_file *filp)
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{
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struct drm_amdgpu_gem_metadata *args = data;
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struct drm_gem_object *gobj;
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struct amdgpu_bo *robj;
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int r = -1;
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DRM_DEBUG("%d \n", args->handle);
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gobj = drm_gem_object_lookup(filp, args->handle);
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if (gobj == NULL)
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return -ENOENT;
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robj = gem_to_amdgpu_bo(gobj);
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r = amdgpu_bo_reserve(robj, false);
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if (unlikely(r != 0))
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goto out;
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|
|
if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) {
|
|
amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info);
|
|
r = amdgpu_bo_get_metadata(robj, args->data.data,
|
|
sizeof(args->data.data),
|
|
&args->data.data_size_bytes,
|
|
&args->data.flags);
|
|
} else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) {
|
|
if (args->data.data_size_bytes > sizeof(args->data.data)) {
|
|
r = -EINVAL;
|
|
goto unreserve;
|
|
}
|
|
r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info);
|
|
if (!r)
|
|
r = amdgpu_bo_set_metadata(robj, args->data.data,
|
|
args->data.data_size_bytes,
|
|
args->data.flags);
|
|
}
|
|
|
|
unreserve:
|
|
amdgpu_bo_unreserve(robj);
|
|
out:
|
|
drm_gem_object_put_unlocked(gobj);
|
|
return r;
|
|
}
|
|
|
|
/**
|
|
* amdgpu_gem_va_update_vm -update the bo_va in its VM
|
|
*
|
|
* @adev: amdgpu_device pointer
|
|
* @vm: vm to update
|
|
* @bo_va: bo_va to update
|
|
* @operation: map, unmap or clear
|
|
*
|
|
* Update the bo_va directly after setting its address. Errors are not
|
|
* vital here, so they are not reported back to userspace.
|
|
*/
|
|
static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
|
|
struct amdgpu_vm *vm,
|
|
struct amdgpu_bo_va *bo_va,
|
|
uint32_t operation)
|
|
{
|
|
int r;
|
|
|
|
if (!amdgpu_vm_ready(vm))
|
|
return;
|
|
|
|
r = amdgpu_vm_clear_freed(adev, vm, NULL);
|
|
if (r)
|
|
goto error;
|
|
|
|
if (operation == AMDGPU_VA_OP_MAP ||
|
|
operation == AMDGPU_VA_OP_REPLACE) {
|
|
r = amdgpu_vm_bo_update(adev, bo_va, false);
|
|
if (r)
|
|
goto error;
|
|
}
|
|
|
|
r = amdgpu_vm_update_directories(adev, vm);
|
|
|
|
error:
|
|
if (r && r != -ERESTARTSYS)
|
|
DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
|
|
}
|
|
|
|
int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *filp)
|
|
{
|
|
const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE |
|
|
AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE |
|
|
AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK;
|
|
const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE |
|
|
AMDGPU_VM_PAGE_PRT;
|
|
|
|
struct drm_amdgpu_gem_va *args = data;
|
|
struct drm_gem_object *gobj;
|
|
struct amdgpu_device *adev = dev->dev_private;
|
|
struct amdgpu_fpriv *fpriv = filp->driver_priv;
|
|
struct amdgpu_bo *abo;
|
|
struct amdgpu_bo_va *bo_va;
|
|
struct amdgpu_bo_list_entry vm_pd;
|
|
struct ttm_validate_buffer tv;
|
|
struct ww_acquire_ctx ticket;
|
|
struct list_head list, duplicates;
|
|
uint64_t va_flags;
|
|
int r = 0;
|
|
|
|
if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
|
|
dev_dbg(&dev->pdev->dev,
|
|
"va_address 0x%LX is in reserved area 0x%LX\n",
|
|
args->va_address, AMDGPU_VA_RESERVED_SIZE);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (args->va_address >= AMDGPU_VA_HOLE_START &&
|
|
args->va_address < AMDGPU_VA_HOLE_END) {
|
|
dev_dbg(&dev->pdev->dev,
|
|
"va_address 0x%LX is in VA hole 0x%LX-0x%LX\n",
|
|
args->va_address, AMDGPU_VA_HOLE_START,
|
|
AMDGPU_VA_HOLE_END);
|
|
return -EINVAL;
|
|
}
|
|
|
|
args->va_address &= AMDGPU_VA_HOLE_MASK;
|
|
|
|
if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {
|
|
dev_dbg(&dev->pdev->dev, "invalid flags combination 0x%08X\n",
|
|
args->flags);
|
|
return -EINVAL;
|
|
}
|
|
|
|
switch (args->operation) {
|
|
case AMDGPU_VA_OP_MAP:
|
|
case AMDGPU_VA_OP_UNMAP:
|
|
case AMDGPU_VA_OP_CLEAR:
|
|
case AMDGPU_VA_OP_REPLACE:
|
|
break;
|
|
default:
|
|
dev_dbg(&dev->pdev->dev, "unsupported operation %d\n",
|
|
args->operation);
|
|
return -EINVAL;
|
|
}
|
|
|
|
INIT_LIST_HEAD(&list);
|
|
INIT_LIST_HEAD(&duplicates);
|
|
if ((args->operation != AMDGPU_VA_OP_CLEAR) &&
|
|
!(args->flags & AMDGPU_VM_PAGE_PRT)) {
|
|
gobj = drm_gem_object_lookup(filp, args->handle);
|
|
if (gobj == NULL)
|
|
return -ENOENT;
|
|
abo = gem_to_amdgpu_bo(gobj);
|
|
tv.bo = &abo->tbo;
|
|
tv.shared = !!(abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID);
|
|
list_add(&tv.head, &list);
|
|
} else {
|
|
gobj = NULL;
|
|
abo = NULL;
|
|
}
|
|
|
|
amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd);
|
|
|
|
r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates);
|
|
if (r)
|
|
goto error_unref;
|
|
|
|
if (abo) {
|
|
bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo);
|
|
if (!bo_va) {
|
|
r = -ENOENT;
|
|
goto error_backoff;
|
|
}
|
|
} else if (args->operation != AMDGPU_VA_OP_CLEAR) {
|
|
bo_va = fpriv->prt_va;
|
|
} else {
|
|
bo_va = NULL;
|
|
}
|
|
|
|
switch (args->operation) {
|
|
case AMDGPU_VA_OP_MAP:
|
|
r = amdgpu_vm_alloc_pts(adev, bo_va->base.vm, args->va_address,
|
|
args->map_size);
|
|
if (r)
|
|
goto error_backoff;
|
|
|
|
va_flags = amdgpu_gmc_get_pte_flags(adev, args->flags);
|
|
r = amdgpu_vm_bo_map(adev, bo_va, args->va_address,
|
|
args->offset_in_bo, args->map_size,
|
|
va_flags);
|
|
break;
|
|
case AMDGPU_VA_OP_UNMAP:
|
|
r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address);
|
|
break;
|
|
|
|
case AMDGPU_VA_OP_CLEAR:
|
|
r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm,
|
|
args->va_address,
|
|
args->map_size);
|
|
break;
|
|
case AMDGPU_VA_OP_REPLACE:
|
|
r = amdgpu_vm_alloc_pts(adev, bo_va->base.vm, args->va_address,
|
|
args->map_size);
|
|
if (r)
|
|
goto error_backoff;
|
|
|
|
va_flags = amdgpu_gmc_get_pte_flags(adev, args->flags);
|
|
r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address,
|
|
args->offset_in_bo, args->map_size,
|
|
va_flags);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !amdgpu_vm_debug)
|
|
amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va,
|
|
args->operation);
|
|
|
|
error_backoff:
|
|
ttm_eu_backoff_reservation(&ticket, &list);
|
|
|
|
error_unref:
|
|
drm_gem_object_put_unlocked(gobj);
|
|
return r;
|
|
}
|
|
|
|
int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *filp)
|
|
{
|
|
struct amdgpu_device *adev = dev->dev_private;
|
|
struct drm_amdgpu_gem_op *args = data;
|
|
struct drm_gem_object *gobj;
|
|
struct amdgpu_bo *robj;
|
|
int r;
|
|
|
|
gobj = drm_gem_object_lookup(filp, args->handle);
|
|
if (gobj == NULL) {
|
|
return -ENOENT;
|
|
}
|
|
robj = gem_to_amdgpu_bo(gobj);
|
|
|
|
r = amdgpu_bo_reserve(robj, false);
|
|
if (unlikely(r))
|
|
goto out;
|
|
|
|
switch (args->op) {
|
|
case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: {
|
|
struct drm_amdgpu_gem_create_in info;
|
|
void __user *out = u64_to_user_ptr(args->value);
|
|
|
|
info.bo_size = robj->gem_base.size;
|
|
info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT;
|
|
info.domains = robj->preferred_domains;
|
|
info.domain_flags = robj->flags;
|
|
amdgpu_bo_unreserve(robj);
|
|
if (copy_to_user(out, &info, sizeof(info)))
|
|
r = -EFAULT;
|
|
break;
|
|
}
|
|
case AMDGPU_GEM_OP_SET_PLACEMENT:
|
|
if (robj->prime_shared_count && (args->value & AMDGPU_GEM_DOMAIN_VRAM)) {
|
|
r = -EINVAL;
|
|
amdgpu_bo_unreserve(robj);
|
|
break;
|
|
}
|
|
if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) {
|
|
r = -EPERM;
|
|
amdgpu_bo_unreserve(robj);
|
|
break;
|
|
}
|
|
robj->preferred_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM |
|
|
AMDGPU_GEM_DOMAIN_GTT |
|
|
AMDGPU_GEM_DOMAIN_CPU);
|
|
robj->allowed_domains = robj->preferred_domains;
|
|
if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
|
|
robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
|
|
|
|
if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
|
|
amdgpu_vm_bo_invalidate(adev, robj, true);
|
|
|
|
amdgpu_bo_unreserve(robj);
|
|
break;
|
|
default:
|
|
amdgpu_bo_unreserve(robj);
|
|
r = -EINVAL;
|
|
}
|
|
|
|
out:
|
|
drm_gem_object_put_unlocked(gobj);
|
|
return r;
|
|
}
|
|
|
|
int amdgpu_mode_dumb_create(struct drm_file *file_priv,
|
|
struct drm_device *dev,
|
|
struct drm_mode_create_dumb *args)
|
|
{
|
|
struct amdgpu_device *adev = dev->dev_private;
|
|
struct drm_gem_object *gobj;
|
|
uint32_t handle;
|
|
u32 domain;
|
|
int r;
|
|
|
|
args->pitch = amdgpu_align_pitch(adev, args->width,
|
|
DIV_ROUND_UP(args->bpp, 8), 0);
|
|
args->size = (u64)args->pitch * args->height;
|
|
args->size = ALIGN(args->size, PAGE_SIZE);
|
|
domain = amdgpu_bo_get_preferred_pin_domain(adev,
|
|
amdgpu_display_supported_domains(adev));
|
|
r = amdgpu_gem_object_create(adev, args->size, 0, domain,
|
|
AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
|
|
ttm_bo_type_device, NULL, &gobj);
|
|
if (r)
|
|
return -ENOMEM;
|
|
|
|
r = drm_gem_handle_create(file_priv, gobj, &handle);
|
|
/* drop reference from allocate - handle holds it now */
|
|
drm_gem_object_put_unlocked(gobj);
|
|
if (r) {
|
|
return r;
|
|
}
|
|
args->handle = handle;
|
|
return 0;
|
|
}
|
|
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
|
|
#define amdgpu_debugfs_gem_bo_print_flag(m, bo, flag) \
|
|
if (bo->flags & (AMDGPU_GEM_CREATE_ ## flag)) { \
|
|
seq_printf((m), " " #flag); \
|
|
}
|
|
|
|
static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, void *data)
|
|
{
|
|
struct drm_gem_object *gobj = ptr;
|
|
struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
|
|
struct seq_file *m = data;
|
|
|
|
struct dma_buf_attachment *attachment;
|
|
struct dma_buf *dma_buf;
|
|
unsigned domain;
|
|
const char *placement;
|
|
unsigned pin_count;
|
|
|
|
domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
|
|
switch (domain) {
|
|
case AMDGPU_GEM_DOMAIN_VRAM:
|
|
placement = "VRAM";
|
|
break;
|
|
case AMDGPU_GEM_DOMAIN_GTT:
|
|
placement = " GTT";
|
|
break;
|
|
case AMDGPU_GEM_DOMAIN_CPU:
|
|
default:
|
|
placement = " CPU";
|
|
break;
|
|
}
|
|
seq_printf(m, "\t0x%08x: %12ld byte %s",
|
|
id, amdgpu_bo_size(bo), placement);
|
|
|
|
pin_count = READ_ONCE(bo->pin_count);
|
|
if (pin_count)
|
|
seq_printf(m, " pin count %d", pin_count);
|
|
|
|
dma_buf = READ_ONCE(bo->gem_base.dma_buf);
|
|
attachment = READ_ONCE(bo->gem_base.import_attach);
|
|
|
|
if (attachment)
|
|
seq_printf(m, " imported from %p", dma_buf);
|
|
else if (dma_buf)
|
|
seq_printf(m, " exported as %p", dma_buf);
|
|
|
|
amdgpu_debugfs_gem_bo_print_flag(m, bo, CPU_ACCESS_REQUIRED);
|
|
amdgpu_debugfs_gem_bo_print_flag(m, bo, NO_CPU_ACCESS);
|
|
amdgpu_debugfs_gem_bo_print_flag(m, bo, CPU_GTT_USWC);
|
|
amdgpu_debugfs_gem_bo_print_flag(m, bo, VRAM_CLEARED);
|
|
amdgpu_debugfs_gem_bo_print_flag(m, bo, SHADOW);
|
|
amdgpu_debugfs_gem_bo_print_flag(m, bo, VRAM_CONTIGUOUS);
|
|
amdgpu_debugfs_gem_bo_print_flag(m, bo, VM_ALWAYS_VALID);
|
|
amdgpu_debugfs_gem_bo_print_flag(m, bo, EXPLICIT_SYNC);
|
|
|
|
seq_printf(m, "\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data)
|
|
{
|
|
struct drm_info_node *node = (struct drm_info_node *)m->private;
|
|
struct drm_device *dev = node->minor->dev;
|
|
struct drm_file *file;
|
|
int r;
|
|
|
|
r = mutex_lock_interruptible(&dev->filelist_mutex);
|
|
if (r)
|
|
return r;
|
|
|
|
list_for_each_entry(file, &dev->filelist, lhead) {
|
|
struct task_struct *task;
|
|
|
|
/*
|
|
* Although we have a valid reference on file->pid, that does
|
|
* not guarantee that the task_struct who called get_pid() is
|
|
* still alive (e.g. get_pid(current) => fork() => exit()).
|
|
* Therefore, we need to protect this ->comm access using RCU.
|
|
*/
|
|
rcu_read_lock();
|
|
task = pid_task(file->pid, PIDTYPE_PID);
|
|
seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid),
|
|
task ? task->comm : "<unknown>");
|
|
rcu_read_unlock();
|
|
|
|
spin_lock(&file->table_lock);
|
|
idr_for_each(&file->object_idr, amdgpu_debugfs_gem_bo_info, m);
|
|
spin_unlock(&file->table_lock);
|
|
}
|
|
|
|
mutex_unlock(&dev->filelist_mutex);
|
|
return 0;
|
|
}
|
|
|
|
static const struct drm_info_list amdgpu_debugfs_gem_list[] = {
|
|
{"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL},
|
|
};
|
|
#endif
|
|
|
|
int amdgpu_debugfs_gem_init(struct amdgpu_device *adev)
|
|
{
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1);
|
|
#endif
|
|
return 0;
|
|
}
|