c783390a0e
Add support for XLR and XLS processors in MIPS Oprofile code. These processors are multi-threaded and have two counters per core. Each counter can track either all the events in the core (global mode), or events in just one thread. We use the counters in the global mode, and use only the first thread in each core to handle the configuration etc. Signed-off-by: Madhusudan Bhat <mbhat@netlogicmicro.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Patchwork: http://patchwork.linux-mips.org/patch/4471 Signed-off-by: John Crispin <blogic@openwrt.org>
441 lines
9.9 KiB
C
441 lines
9.9 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2004, 05, 06 by Ralf Baechle
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* Copyright (C) 2005 by MIPS Technologies, Inc.
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*/
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#include <linux/cpumask.h>
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#include <linux/oprofile.h>
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#include <linux/interrupt.h>
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#include <linux/smp.h>
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#include <asm/irq_regs.h>
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#include "op_impl.h"
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#define M_PERFCTL_EXL (1UL << 0)
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#define M_PERFCTL_KERNEL (1UL << 1)
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#define M_PERFCTL_SUPERVISOR (1UL << 2)
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#define M_PERFCTL_USER (1UL << 3)
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#define M_PERFCTL_INTERRUPT_ENABLE (1UL << 4)
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#define M_PERFCTL_EVENT(event) (((event) & 0x3ff) << 5)
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#define M_PERFCTL_VPEID(vpe) ((vpe) << 16)
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#define M_PERFCTL_MT_EN(filter) ((filter) << 20)
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#define M_TC_EN_ALL M_PERFCTL_MT_EN(0)
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#define M_TC_EN_VPE M_PERFCTL_MT_EN(1)
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#define M_TC_EN_TC M_PERFCTL_MT_EN(2)
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#define M_PERFCTL_TCID(tcid) ((tcid) << 22)
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#define M_PERFCTL_WIDE (1UL << 30)
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#define M_PERFCTL_MORE (1UL << 31)
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#define M_COUNTER_OVERFLOW (1UL << 31)
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/* Netlogic XLR specific, count events in all threads in a core */
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#define M_PERFCTL_COUNT_ALL_THREADS (1UL << 13)
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static int (*save_perf_irq)(void);
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/*
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* XLR has only one set of counters per core. Designate the
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* first hardware thread in the core for setup and init.
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* Skip CPUs with non-zero hardware thread id (4 hwt per core)
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*/
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#ifdef CONFIG_CPU_XLR
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#define oprofile_skip_cpu(c) ((cpu_logical_map(c) & 0x3) != 0)
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#else
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#define oprofile_skip_cpu(c) 0
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#endif
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#ifdef CONFIG_MIPS_MT_SMP
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static int cpu_has_mipsmt_pertccounters;
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#define WHAT (M_TC_EN_VPE | \
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M_PERFCTL_VPEID(cpu_data[smp_processor_id()].vpe_id))
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#define vpe_id() (cpu_has_mipsmt_pertccounters ? \
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0 : cpu_data[smp_processor_id()].vpe_id)
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/*
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* The number of bits to shift to convert between counters per core and
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* counters per VPE. There is no reasonable interface atm to obtain the
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* number of VPEs used by Linux and in the 34K this number is fixed to two
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* anyways so we hardcore a few things here for the moment. The way it's
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* done here will ensure that oprofile VSMP kernel will run right on a lesser
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* core like a 24K also or with maxcpus=1.
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*/
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static inline unsigned int vpe_shift(void)
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{
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if (num_possible_cpus() > 1)
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return 1;
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return 0;
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}
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#else
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#define WHAT 0
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#define vpe_id() 0
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static inline unsigned int vpe_shift(void)
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{
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return 0;
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}
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#endif
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static inline unsigned int counters_total_to_per_cpu(unsigned int counters)
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{
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return counters >> vpe_shift();
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}
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static inline unsigned int counters_per_cpu_to_total(unsigned int counters)
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{
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return counters << vpe_shift();
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}
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#define __define_perf_accessors(r, n, np) \
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\
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static inline unsigned int r_c0_ ## r ## n(void) \
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{ \
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unsigned int cpu = vpe_id(); \
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\
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switch (cpu) { \
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case 0: \
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return read_c0_ ## r ## n(); \
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case 1: \
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return read_c0_ ## r ## np(); \
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default: \
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BUG(); \
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} \
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return 0; \
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} \
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\
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static inline void w_c0_ ## r ## n(unsigned int value) \
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{ \
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unsigned int cpu = vpe_id(); \
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\
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switch (cpu) { \
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case 0: \
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write_c0_ ## r ## n(value); \
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return; \
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case 1: \
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write_c0_ ## r ## np(value); \
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return; \
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default: \
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BUG(); \
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} \
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return; \
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} \
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__define_perf_accessors(perfcntr, 0, 2)
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__define_perf_accessors(perfcntr, 1, 3)
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__define_perf_accessors(perfcntr, 2, 0)
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__define_perf_accessors(perfcntr, 3, 1)
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__define_perf_accessors(perfctrl, 0, 2)
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__define_perf_accessors(perfctrl, 1, 3)
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__define_perf_accessors(perfctrl, 2, 0)
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__define_perf_accessors(perfctrl, 3, 1)
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struct op_mips_model op_model_mipsxx_ops;
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static struct mipsxx_register_config {
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unsigned int control[4];
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unsigned int counter[4];
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} reg;
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/* Compute all of the registers in preparation for enabling profiling. */
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static void mipsxx_reg_setup(struct op_counter_config *ctr)
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{
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unsigned int counters = op_model_mipsxx_ops.num_counters;
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int i;
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/* Compute the performance counter control word. */
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for (i = 0; i < counters; i++) {
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reg.control[i] = 0;
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reg.counter[i] = 0;
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if (!ctr[i].enabled)
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continue;
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reg.control[i] = M_PERFCTL_EVENT(ctr[i].event) |
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M_PERFCTL_INTERRUPT_ENABLE;
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if (ctr[i].kernel)
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reg.control[i] |= M_PERFCTL_KERNEL;
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if (ctr[i].user)
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reg.control[i] |= M_PERFCTL_USER;
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if (ctr[i].exl)
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reg.control[i] |= M_PERFCTL_EXL;
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if (current_cpu_type() == CPU_XLR)
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reg.control[i] |= M_PERFCTL_COUNT_ALL_THREADS;
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reg.counter[i] = 0x80000000 - ctr[i].count;
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}
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}
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/* Program all of the registers in preparation for enabling profiling. */
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static void mipsxx_cpu_setup(void *args)
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{
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unsigned int counters = op_model_mipsxx_ops.num_counters;
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if (oprofile_skip_cpu(smp_processor_id()))
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return;
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switch (counters) {
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case 4:
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w_c0_perfctrl3(0);
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w_c0_perfcntr3(reg.counter[3]);
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case 3:
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w_c0_perfctrl2(0);
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w_c0_perfcntr2(reg.counter[2]);
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case 2:
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w_c0_perfctrl1(0);
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w_c0_perfcntr1(reg.counter[1]);
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case 1:
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w_c0_perfctrl0(0);
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w_c0_perfcntr0(reg.counter[0]);
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}
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}
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/* Start all counters on current CPU */
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static void mipsxx_cpu_start(void *args)
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{
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unsigned int counters = op_model_mipsxx_ops.num_counters;
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if (oprofile_skip_cpu(smp_processor_id()))
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return;
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switch (counters) {
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case 4:
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w_c0_perfctrl3(WHAT | reg.control[3]);
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case 3:
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w_c0_perfctrl2(WHAT | reg.control[2]);
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case 2:
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w_c0_perfctrl1(WHAT | reg.control[1]);
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case 1:
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w_c0_perfctrl0(WHAT | reg.control[0]);
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}
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}
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/* Stop all counters on current CPU */
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static void mipsxx_cpu_stop(void *args)
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{
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unsigned int counters = op_model_mipsxx_ops.num_counters;
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if (oprofile_skip_cpu(smp_processor_id()))
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return;
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switch (counters) {
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case 4:
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w_c0_perfctrl3(0);
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case 3:
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w_c0_perfctrl2(0);
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case 2:
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w_c0_perfctrl1(0);
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case 1:
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w_c0_perfctrl0(0);
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}
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}
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static int mipsxx_perfcount_handler(void)
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{
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unsigned int counters = op_model_mipsxx_ops.num_counters;
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unsigned int control;
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unsigned int counter;
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int handled = IRQ_NONE;
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if (cpu_has_mips_r2 && !(read_c0_cause() & (1 << 26)))
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return handled;
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switch (counters) {
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#define HANDLE_COUNTER(n) \
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case n + 1: \
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control = r_c0_perfctrl ## n(); \
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counter = r_c0_perfcntr ## n(); \
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if ((control & M_PERFCTL_INTERRUPT_ENABLE) && \
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(counter & M_COUNTER_OVERFLOW)) { \
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oprofile_add_sample(get_irq_regs(), n); \
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w_c0_perfcntr ## n(reg.counter[n]); \
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handled = IRQ_HANDLED; \
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}
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HANDLE_COUNTER(3)
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HANDLE_COUNTER(2)
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HANDLE_COUNTER(1)
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HANDLE_COUNTER(0)
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}
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return handled;
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}
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#define M_CONFIG1_PC (1 << 4)
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static inline int __n_counters(void)
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{
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if (!(read_c0_config1() & M_CONFIG1_PC))
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return 0;
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if (!(read_c0_perfctrl0() & M_PERFCTL_MORE))
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return 1;
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if (!(read_c0_perfctrl1() & M_PERFCTL_MORE))
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return 2;
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if (!(read_c0_perfctrl2() & M_PERFCTL_MORE))
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return 3;
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return 4;
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}
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static inline int n_counters(void)
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{
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int counters;
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switch (current_cpu_type()) {
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case CPU_R10000:
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counters = 2;
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break;
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case CPU_R12000:
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case CPU_R14000:
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counters = 4;
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break;
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default:
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counters = __n_counters();
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}
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return counters;
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}
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static void reset_counters(void *arg)
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{
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int counters = (int)(long)arg;
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switch (counters) {
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case 4:
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w_c0_perfctrl3(0);
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w_c0_perfcntr3(0);
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case 3:
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w_c0_perfctrl2(0);
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w_c0_perfcntr2(0);
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case 2:
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w_c0_perfctrl1(0);
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w_c0_perfcntr1(0);
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case 1:
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w_c0_perfctrl0(0);
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w_c0_perfcntr0(0);
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}
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}
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static irqreturn_t mipsxx_perfcount_int(int irq, void *dev_id)
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{
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return mipsxx_perfcount_handler();
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}
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static int __init mipsxx_init(void)
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{
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int counters;
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counters = n_counters();
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if (counters == 0) {
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printk(KERN_ERR "Oprofile: CPU has no performance counters\n");
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return -ENODEV;
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}
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#ifdef CONFIG_MIPS_MT_SMP
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cpu_has_mipsmt_pertccounters = read_c0_config7() & (1<<19);
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if (!cpu_has_mipsmt_pertccounters)
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counters = counters_total_to_per_cpu(counters);
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#endif
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on_each_cpu(reset_counters, (void *)(long)counters, 1);
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op_model_mipsxx_ops.num_counters = counters;
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switch (current_cpu_type()) {
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case CPU_M14KC:
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op_model_mipsxx_ops.cpu_type = "mips/M14Kc";
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break;
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case CPU_20KC:
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op_model_mipsxx_ops.cpu_type = "mips/20K";
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break;
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case CPU_24K:
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op_model_mipsxx_ops.cpu_type = "mips/24K";
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break;
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case CPU_25KF:
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op_model_mipsxx_ops.cpu_type = "mips/25K";
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break;
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case CPU_1004K:
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case CPU_34K:
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op_model_mipsxx_ops.cpu_type = "mips/34K";
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break;
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case CPU_74K:
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op_model_mipsxx_ops.cpu_type = "mips/74K";
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break;
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case CPU_5KC:
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op_model_mipsxx_ops.cpu_type = "mips/5K";
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break;
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case CPU_R10000:
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if ((current_cpu_data.processor_id & 0xff) == 0x20)
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op_model_mipsxx_ops.cpu_type = "mips/r10000-v2.x";
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else
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op_model_mipsxx_ops.cpu_type = "mips/r10000";
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break;
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case CPU_R12000:
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case CPU_R14000:
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op_model_mipsxx_ops.cpu_type = "mips/r12000";
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break;
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case CPU_SB1:
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case CPU_SB1A:
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op_model_mipsxx_ops.cpu_type = "mips/sb1";
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break;
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case CPU_LOONGSON1:
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op_model_mipsxx_ops.cpu_type = "mips/loongson1";
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break;
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case CPU_XLR:
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op_model_mipsxx_ops.cpu_type = "mips/xlr";
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break;
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default:
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printk(KERN_ERR "Profiling unsupported for this CPU\n");
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return -ENODEV;
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}
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save_perf_irq = perf_irq;
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perf_irq = mipsxx_perfcount_handler;
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if ((cp0_perfcount_irq >= 0) && (cp0_compare_irq != cp0_perfcount_irq))
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return request_irq(cp0_perfcount_irq, mipsxx_perfcount_int,
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0, "Perfcounter", save_perf_irq);
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return 0;
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}
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static void mipsxx_exit(void)
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{
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int counters = op_model_mipsxx_ops.num_counters;
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if ((cp0_perfcount_irq >= 0) && (cp0_compare_irq != cp0_perfcount_irq))
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free_irq(cp0_perfcount_irq, save_perf_irq);
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counters = counters_per_cpu_to_total(counters);
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on_each_cpu(reset_counters, (void *)(long)counters, 1);
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perf_irq = save_perf_irq;
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}
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struct op_mips_model op_model_mipsxx_ops = {
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.reg_setup = mipsxx_reg_setup,
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.cpu_setup = mipsxx_cpu_setup,
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.init = mipsxx_init,
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.exit = mipsxx_exit,
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.cpu_start = mipsxx_cpu_start,
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.cpu_stop = mipsxx_cpu_stop,
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};
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