86f5362e7a
The commit d0a0ce3e77 ("thermal: exynos: Add
missing definations and code cleanup") has removed setting of test MUX address
value at TMU configuration setting.
This field is not present on Exynos4210 and Exynos5 SoCs. However on Exynos4412
SoC it is required to set this field after reset because without it TMU shows
maximal available temperature, which causes immediate platform shutdown.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com>
167 lines
5.7 KiB
C
167 lines
5.7 KiB
C
/*
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* exynos_tmu_data.h - Samsung EXYNOS tmu data header file
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*
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* Copyright (C) 2013 Samsung Electronics
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* Amit Daniel Kachhap <amit.daniel@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#ifndef _EXYNOS_TMU_DATA_H
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#define _EXYNOS_TMU_DATA_H
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/* Exynos generic registers */
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#define EXYNOS_TMU_REG_TRIMINFO 0x0
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#define EXYNOS_TMU_REG_CONTROL 0x20
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#define EXYNOS_TMU_REG_STATUS 0x28
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#define EXYNOS_TMU_REG_CURRENT_TEMP 0x40
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#define EXYNOS_TMU_REG_INTEN 0x70
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#define EXYNOS_TMU_REG_INTSTAT 0x74
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#define EXYNOS_TMU_REG_INTCLEAR 0x78
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#define EXYNOS_TMU_TEMP_MASK 0xff
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#define EXYNOS_TMU_REF_VOLTAGE_SHIFT 24
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#define EXYNOS_TMU_REF_VOLTAGE_MASK 0x1f
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#define EXYNOS_TMU_BUF_SLOPE_SEL_MASK 0xf
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#define EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT 8
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#define EXYNOS_TMU_CORE_EN_SHIFT 0
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/* Exynos4210 specific registers */
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#define EXYNOS4210_TMU_REG_THRESHOLD_TEMP 0x44
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#define EXYNOS4210_TMU_REG_TRIG_LEVEL0 0x50
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#define EXYNOS4210_TMU_REG_TRIG_LEVEL1 0x54
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#define EXYNOS4210_TMU_REG_TRIG_LEVEL2 0x58
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#define EXYNOS4210_TMU_REG_TRIG_LEVEL3 0x5C
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#define EXYNOS4210_TMU_REG_PAST_TEMP0 0x60
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#define EXYNOS4210_TMU_REG_PAST_TEMP1 0x64
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#define EXYNOS4210_TMU_REG_PAST_TEMP2 0x68
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#define EXYNOS4210_TMU_REG_PAST_TEMP3 0x6C
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#define EXYNOS4210_TMU_TRIG_LEVEL0_MASK 0x1
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#define EXYNOS4210_TMU_TRIG_LEVEL1_MASK 0x10
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#define EXYNOS4210_TMU_TRIG_LEVEL2_MASK 0x100
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#define EXYNOS4210_TMU_TRIG_LEVEL3_MASK 0x1000
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#define EXYNOS4210_TMU_TRIG_LEVEL_MASK 0x1111
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#define EXYNOS4210_TMU_INTCLEAR_VAL 0x1111
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/* Exynos5250 and Exynos4412 specific registers */
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#define EXYNOS_TMU_TRIMINFO_CON 0x14
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#define EXYNOS_THD_TEMP_RISE 0x50
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#define EXYNOS_THD_TEMP_FALL 0x54
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#define EXYNOS_EMUL_CON 0x80
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#define EXYNOS_TRIMINFO_RELOAD_SHIFT 1
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#define EXYNOS_TRIMINFO_25_SHIFT 0
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#define EXYNOS_TRIMINFO_85_SHIFT 8
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#define EXYNOS_TMU_RISE_INT_MASK 0x111
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#define EXYNOS_TMU_RISE_INT_SHIFT 0
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#define EXYNOS_TMU_FALL_INT_MASK 0x111
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#define EXYNOS_TMU_FALL_INT_SHIFT 12
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#define EXYNOS_TMU_CLEAR_RISE_INT 0x111
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#define EXYNOS_TMU_CLEAR_FALL_INT (0x111 << 12)
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#define EXYNOS_TMU_TRIP_MODE_SHIFT 13
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#define EXYNOS_TMU_TRIP_MODE_MASK 0x7
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#define EXYNOS_TMU_THERM_TRIP_EN_SHIFT 12
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#define EXYNOS_TMU_CALIB_MODE_SHIFT 4
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#define EXYNOS_TMU_CALIB_MODE_MASK 0x3
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#define EXYNOS_TMU_INTEN_RISE0_SHIFT 0
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#define EXYNOS_TMU_INTEN_RISE1_SHIFT 4
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#define EXYNOS_TMU_INTEN_RISE2_SHIFT 8
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#define EXYNOS_TMU_INTEN_RISE3_SHIFT 12
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#define EXYNOS_TMU_INTEN_FALL0_SHIFT 16
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#define EXYNOS_TMU_INTEN_FALL1_SHIFT 20
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#define EXYNOS_TMU_INTEN_FALL2_SHIFT 24
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#define EXYNOS_EMUL_TIME 0x57F0
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#define EXYNOS_EMUL_TIME_MASK 0xffff
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#define EXYNOS_EMUL_TIME_SHIFT 16
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#define EXYNOS_EMUL_DATA_SHIFT 8
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#define EXYNOS_EMUL_DATA_MASK 0xFF
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#define EXYNOS_EMUL_ENABLE 0x1
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#define EXYNOS_MAX_TRIGGER_PER_REG 4
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/* Exynos4412 specific */
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#define EXYNOS4412_MUX_ADDR_VALUE 6
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#define EXYNOS4412_MUX_ADDR_SHIFT 20
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/*exynos5440 specific registers*/
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#define EXYNOS5440_TMU_S0_7_TRIM 0x000
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#define EXYNOS5440_TMU_S0_7_CTRL 0x020
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#define EXYNOS5440_TMU_S0_7_DEBUG 0x040
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#define EXYNOS5440_TMU_S0_7_STATUS 0x060
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#define EXYNOS5440_TMU_S0_7_TEMP 0x0f0
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#define EXYNOS5440_TMU_S0_7_TH0 0x110
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#define EXYNOS5440_TMU_S0_7_TH1 0x130
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#define EXYNOS5440_TMU_S0_7_TH2 0x150
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#define EXYNOS5440_TMU_S0_7_EVTEN 0x1F0
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#define EXYNOS5440_TMU_S0_7_IRQEN 0x210
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#define EXYNOS5440_TMU_S0_7_IRQ 0x230
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/* exynos5440 common registers */
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#define EXYNOS5440_TMU_IRQ_STATUS 0x000
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#define EXYNOS5440_TMU_PMIN 0x004
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#define EXYNOS5440_TMU_TEMP 0x008
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#define EXYNOS5440_TMU_RISE_INT_MASK 0xf
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#define EXYNOS5440_TMU_RISE_INT_SHIFT 0
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#define EXYNOS5440_TMU_FALL_INT_MASK 0xf
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#define EXYNOS5440_TMU_FALL_INT_SHIFT 4
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#define EXYNOS5440_TMU_INTEN_RISE0_SHIFT 0
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#define EXYNOS5440_TMU_INTEN_RISE1_SHIFT 1
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#define EXYNOS5440_TMU_INTEN_RISE2_SHIFT 2
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#define EXYNOS5440_TMU_INTEN_RISE3_SHIFT 3
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#define EXYNOS5440_TMU_INTEN_FALL0_SHIFT 4
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#define EXYNOS5440_TMU_INTEN_FALL1_SHIFT 5
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#define EXYNOS5440_TMU_INTEN_FALL2_SHIFT 6
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#define EXYNOS5440_TMU_INTEN_FALL3_SHIFT 7
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#define EXYNOS5440_TMU_TH_RISE0_SHIFT 0
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#define EXYNOS5440_TMU_TH_RISE1_SHIFT 8
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#define EXYNOS5440_TMU_TH_RISE2_SHIFT 16
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#define EXYNOS5440_TMU_TH_RISE3_SHIFT 24
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#define EXYNOS5440_TMU_TH_RISE4_SHIFT 24
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#define EXYNOS5440_EFUSE_SWAP_OFFSET 8
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#if defined(CONFIG_CPU_EXYNOS4210)
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extern struct exynos_tmu_init_data const exynos4210_default_tmu_data;
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#define EXYNOS4210_TMU_DRV_DATA (&exynos4210_default_tmu_data)
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#else
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#define EXYNOS4210_TMU_DRV_DATA (NULL)
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#endif
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#if defined(CONFIG_SOC_EXYNOS4412)
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extern struct exynos_tmu_init_data const exynos4412_default_tmu_data;
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#define EXYNOS4412_TMU_DRV_DATA (&exynos4412_default_tmu_data)
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#else
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#define EXYNOS4412_TMU_DRV_DATA (NULL)
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#endif
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#if defined(CONFIG_SOC_EXYNOS5250)
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extern struct exynos_tmu_init_data const exynos5250_default_tmu_data;
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#define EXYNOS5250_TMU_DRV_DATA (&exynos5250_default_tmu_data)
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#else
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#define EXYNOS5250_TMU_DRV_DATA (NULL)
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#endif
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#if defined(CONFIG_SOC_EXYNOS5440)
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extern struct exynos_tmu_init_data const exynos5440_default_tmu_data;
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#define EXYNOS5440_TMU_DRV_DATA (&exynos5440_default_tmu_data)
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#else
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#define EXYNOS5440_TMU_DRV_DATA (NULL)
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#endif
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#endif /*_EXYNOS_TMU_DATA_H*/
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