a12cf0a8c6
The version 2 ColdFire CPU based cores all contain a similar cache controller unit. Create a set of bit flag definitions for the supporting registers. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
57 lines
2.4 KiB
C
57 lines
2.4 KiB
C
/****************************************************************************/
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/*
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* m52xxacr.h -- ColdFire version 2 core cache support
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*
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* (C) Copyright 2010, Greg Ungerer <gerg@snapgear.com>
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*/
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/****************************************************************************/
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#ifndef m52xxacr_h
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#define m52xxacr_h
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/****************************************************************************/
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/*
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* All varients of the ColdFire using version 2 cores have a similar
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* cache setup. Although not absolutely identical the cache register
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* definitions are compatible for all of them. Mostly they support a
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* configurable cache memory that can be instruction only, data only,
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* or split instruction and data. The exception is the very old version 2
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* core based parts, like the 5206(e), 5249 and 5272, which are instruction
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* cache only. Cache size varies from 2k up to 16k.
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*/
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/*
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* Define the Cache Control register flags.
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*/
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#define CACR_CENB 0x80000000 /* Enable cache */
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#define CACR_CDPI 0x10000000 /* Disable invalidation by CPUSHL */
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#define CACR_CFRZ 0x08000000 /* Cache freeze mode */
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#define CACR_CINV 0x01000000 /* Invalidate cache */
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#define CACR_DISI 0x00800000 /* Disable instruction cache */
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#define CACR_DISD 0x00400000 /* Disable data cache */
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#define CACR_INVI 0x00200000 /* Invalidate instruction cache */
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#define CACR_INVD 0x00100000 /* Invalidate data cache */
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#define CACR_CEIB 0x00000400 /* Non-cachable instruction burst */
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#define CACR_DCM 0x00000200 /* Default cache mode */
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#define CACR_DBWE 0x00000100 /* Buffered write enable */
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#define CACR_DWP 0x00000020 /* Write protection */
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#define CACR_EUSP 0x00000010 /* Enable separate user a7 */
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/*
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* Define the Access Control register flags.
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*/
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#define ACR_BASE_POS 24 /* Address Base (upper 8 bits) */
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#define ACR_MASK_POS 16 /* Address Mask (next 8 bits) */
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#define ACR_ENABLE 0x00008000 /* Enable this ACR */
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#define ACR_USER 0x00000000 /* Allow only user accesses */
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#define ACR_SUPER 0x00002000 /* Allow supervisor access only */
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#define ACR_ANY 0x00004000 /* Allow any access type */
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#define ACR_CENB 0x00000000 /* Caching of region enabled */
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#define ACR_CDIS 0x00000040 /* Caching of region disabled */
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#define ACR_BWE 0x00000020 /* Write buffer enabled */
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#define ACR_WPROTECT 0x00000004 /* Write protect region */
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/****************************************************************************/
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#endif /* m52xxsim_h */
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